diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-03-01 12:31:07 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:29:46 +0300 |
| commit | 043790f3edb554f8db3e841fd17a33b622bc2b31 (patch) | |
| tree | 3e542f26c1aeafc693d7add3877cde3b54733961 /drivers/gpu/drm/xe/xe_hw_engine_types.h | |
| parent | 4c128558fe16b77013a251bcc3af8caa77fb7732 (diff) | |
| download | linux-043790f3edb554f8db3e841fd17a33b622bc2b31.tar.xz | |
drm/xe/rtp: Add match for render reset domain
This allows to create WA/tuning rules that match the first engine that
is either of compute or render class. This matters for platforms that
don't have a render engine and that may have arbitrary compute engines
fused off: some register programming need to be added to one of those
engines.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_hw_engine_types.h')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_hw_engine_types.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h index 05a2fdc381d7..2c40384957da 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h @@ -23,6 +23,7 @@ enum xe_engine_class { enum xe_hw_engine_id { XE_HW_ENGINE_RCS0, +#define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0) XE_HW_ENGINE_BCS0, XE_HW_ENGINE_BCS1, XE_HW_ENGINE_BCS2, @@ -32,6 +33,7 @@ enum xe_hw_engine_id { XE_HW_ENGINE_BCS6, XE_HW_ENGINE_BCS7, XE_HW_ENGINE_BCS8, +#define XE_HW_ENGINE_BCS_MASK GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0) XE_HW_ENGINE_VCS0, XE_HW_ENGINE_VCS1, XE_HW_ENGINE_VCS2, @@ -40,14 +42,17 @@ enum xe_hw_engine_id { XE_HW_ENGINE_VCS5, XE_HW_ENGINE_VCS6, XE_HW_ENGINE_VCS7, +#define XE_HW_ENGINE_VCS_MASK GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) XE_HW_ENGINE_VECS0, XE_HW_ENGINE_VECS1, XE_HW_ENGINE_VECS2, XE_HW_ENGINE_VECS3, +#define XE_HW_ENGINE_VECS_MASK GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) XE_HW_ENGINE_CCS0, XE_HW_ENGINE_CCS1, XE_HW_ENGINE_CCS2, XE_HW_ENGINE_CCS3, +#define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) XE_NUM_HW_ENGINES, }; |