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authorGuenter Roeck <linux@roeck-us.net>2012-01-19 23:02:18 +0400
committerGuenter Roeck <guenter.roeck@ericsson.com>2012-03-19 05:26:53 +0400
commit86d566e58edc578f12fe070e1671944889e4d391 (patch)
tree678c44f0b142791dc4f049f86c08804af4f51b2b /drivers/hwmon/hwmon-vid.c
parent5ed04880a3399a0bb0bb5eb886316b8a722b1a7b (diff)
downloadlinux-86d566e58edc578f12fe070e1671944889e4d391.tar.xz
hwmon: (hwmon-vid) Fix multi-line comments
Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'drivers/hwmon/hwmon-vid.c')
-rw-r--r--drivers/hwmon/hwmon-vid.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
index 4fcb867122ec..4029ac618d71 100644
--- a/drivers/hwmon/hwmon-vid.c
+++ b/drivers/hwmon/hwmon-vid.c
@@ -40,7 +40,7 @@
* available at http://developer.intel.com/.
*
* AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
- * http://support.amd.com/us/Processor_TechDocs/26094.PDF
+ * http://support.amd.com/us/Processor_TechDocs/26094.PDF
* Table 74. VID Code Voltages
* This corresponds to an arbitrary VRM code of 24 in the functions below.
* These CPU models (K8 revision <= E) have 5 VID pins. See also:
@@ -185,10 +185,12 @@ struct vrm_model {
static struct vrm_model vrm_models[] = {
{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
- /* In theory, all NPT family 0Fh processors have 6 VID pins and should
- thus use vrm 25, however in practice not all mainboards route the
- 6th VID pin because it is never needed. So we use the 5 VID pin
- variant (vrm 24) for the models which exist today. */
+ /*
+ * In theory, all NPT family 0Fh processors have 6 VID pins and should
+ * thus use vrm 25, however in practice not all mainboards route the
+ * 6th VID pin because it is never needed. So we use the 5 VID pin
+ * variant (vrm 24) for the models which exist today.
+ */
{X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */
{X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */
{X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */