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| author | Lu Baolu <baolu.lu@linux.intel.com> | 2020-06-23 02:13:40 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2020-06-23 11:08:31 +0300 |
| commit | 9486727f5981a5ec5c0b699fb1777451bd6786e4 (patch) | |
| tree | c0c193c3357c754087fa5c6e93ebc4f9bbd1722f /drivers/iommu/arm-smmu.c | |
| parent | 48778464bb7d346b47157d21ffde2af6b2d39110 (diff) | |
| download | linux-9486727f5981a5ec5c0b699fb1777451bd6786e4.tar.xz | |
iommu/vt-d: Make Intel SVM code 64-bit only
Current Intel SVM is designed by setting the pgd_t of the processor page
table to FLPTR field of the PASID entry. The first level translation only
supports 4 and 5 level paging structures, hence it's infeasible for the
IOMMU to share a processor's page table when it's running in 32-bit mode.
Let's disable 32bit support for now and claim support only when all the
missing pieces are ready in the future.
Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode")
Suggested-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20200622231345.29722-2-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/arm-smmu.c')
0 files changed, 0 insertions, 0 deletions