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authorDmitry Osipenko <digetx@gmail.com>2021-10-07 01:46:59 +0300
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-10-15 10:52:47 +0300
commit131dd9a436d8f6dbaf3d9597803765d271b2fc19 (patch)
treee806729af20c5fb202c03fa4f30a228a9e676145 /drivers/memory/tegra/Kconfig
parent38322cf423f69b89b6e0eaad4017ab41cfe45b45 (diff)
downloadlinux-131dd9a436d8f6dbaf3d9597803765d271b2fc19.tar.xz
memory: tegra20-emc: Support matching timings by LPDDR2 configuration
ASUS Transformer TF101 doesn't provide RAM code and in this case memory timings should be selected based on identity information read out from SDRAM chip. Support matching timings by LPDDR2 configuration. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20211006224659.21434-10-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'drivers/memory/tegra/Kconfig')
-rw-r--r--drivers/memory/tegra/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index f9bae36c03a3..7951764b4efe 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -16,6 +16,7 @@ config TEGRA20_EMC
depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
select DEVFREQ_GOV_SIMPLE_ONDEMAND
select PM_DEVFREQ
+ select DDR
help
This driver is for the External Memory Controller (EMC) found on
Tegra20 chips. The EMC controls the external DRAM on the board.