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authorLinu Cherian <lcherian@marvell.com>2018-11-22 14:48:35 +0300
committerDavid S. Miller <davem@davemloft.net>2018-11-24 04:23:25 +0300
commit12e4c9ab2eb3244f9f90b595bb4b988e4d423c62 (patch)
treea095a5d2f14ad97d21fa4404961f0f7244658239 /drivers/net/ethernet/marvell/octeontx2/af/cgx.h
parent44990aaa939439cfd151435e5dcd965494ace8b0 (diff)
downloadlinux-12e4c9ab2eb3244f9f90b595bb4b988e4d423c62.tar.xz
octeontx2-af: Handle non-contiguous CGX LMAC interfaces
For this, cgx_id(struct cgx) definition has been changed to reflect cgx port id instead of device instance id. Now cgx_id can be directly used as channel offset for NPC configuration. Assumptions on contiguous cgx port ids has been removed from nix_calibrate_x2p as well. As a side effect, allocation of conversion tables that were based on cgx count are changed to cgx port id max value. Tables would return NULL for invalid cgx ports. Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/cgx.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/af/cgx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
index 8d7d77b3035c..5f186e4307b1 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
@@ -20,7 +20,7 @@
/* PCI BAR nos */
#define PCI_CFG_REG_BAR_NUM 0
-#define MAX_CGX 3
+#define CGX_ID_MASK 0x7
#define MAX_LMAC_PER_CGX 4
#define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */
#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
@@ -95,7 +95,7 @@ struct cgx_event_cb {
extern struct pci_driver cgx_driver;
-int cgx_get_cgx_cnt(void);
+int cgx_get_cgxcnt_max(void);
int cgx_get_lmac_cnt(void *cgxd);
void *cgx_get_pdata(int cgx_id);
int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);