summaryrefslogtreecommitdiff
path: root/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
diff options
context:
space:
mode:
authorSunil Goutham <sgoutham@marvell.com>2023-06-12 09:04:21 +0300
committerDavid S. Miller <davem@davemloft.net>2023-06-13 11:54:57 +0300
commitbbba125eade7916277ef694d562cc95a39e86487 (patch)
tree78101b87a7a7f6aa225be29d0864657ae622169d /drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
parent79bc788c038c9c87224d41ba6bbab20b6bf1a141 (diff)
downloadlinux-bbba125eade7916277ef694d562cc95a39e86487.tar.xz
octeontx2-af: cn10k: Set NIX DWRR MTU for CN10KB silicon
The DWRR MTU config added for SDP and RPM/LBK links on CN10K silicon is further extended on CK10KB silicon variant and made it configurable. Now there are 4 DWRR MTU config to choose while setting transmit scheduler's RR_WEIGHT. Here we are reserving one config for each of RPM, SDP and LBK. NIXX_AF_DWRR_MTUX(0) ---> RPM NIXX_AF_DWRR_MTUX(1) ---> SDP NIXX_AF_DWRR_MTUX(2) ---> LBK PF/VF drivers can choose the DWRR_MTU to be used by setting SMQX_CFG[pkt_link_type] to one of above. TLx_SCHEDULE[RR_WEIGHT] is to be as configured 'quantum / 2^DWRR_MTUX[MTU]'. DWRR_MTU of each link is exposed to PF/VF drivers via mailbox for RR_WEIGHT calculation. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
index a9ed15d1793a..ba8091131ec0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
@@ -227,6 +227,7 @@ struct otx2_hw {
u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
u16 matchall_ipolicer;
u32 dwrr_mtu;
+ u8 smq_link_type;
/* HW settings, coalescing etc */
u16 rx_chan_base;