diff options
| author | Bitterblue Smith <rtl8821cerfe2@gmail.com> | 2023-05-13 23:47:38 +0300 |
|---|---|---|
| committer | Kalle Valo <kvalo@kernel.org> | 2023-05-15 21:25:48 +0300 |
| commit | c98411dc8cf6c15b8dbbfb37475bcc08b8958880 (patch) | |
| tree | 8a86e1d9ef694165876dffe9a046299c16c640dd /drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | |
| parent | 87807f77a03d0271211b75f84b2a8b88f4e8e5d4 (diff) | |
| download | linux-c98411dc8cf6c15b8dbbfb37475bcc08b8958880.tar.xz | |
wifi: rtl8xxxu: Support new chip RTL8192FU
This is a newer chip, similar to the RTL8710BU in that it uses the same
PHY status structs.
Features: 2.4 GHz, b/g/n mode, 2T2R, 300 Mbps.
It can allegedly have Bluetooth, but that's not implemented here.
This chip can have many RFE (RF front end) types, of which types 1
and 5 are the only ones tested. Many of the other types need different
initialisation tables. They can be added if someone wants them.
The vendor driver v5.8.6.2_35538.20191028_COEX20190910-0d02 from
https://github.com/BrightX/rtl8192fu was used as reference, with
additional device IDs taken from
https://github.com/kelebek333/rtl8192fu-dkms.
The vendor driver also claims to support devices with ID 0bda:a725,
but that is found in some bluetooth-only devices, so it's not supported
here.
Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Reviewed-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/7dcf9fb9-1c97-ac28-5286-2236e287a18c@gmail.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h index 8571d5129f32..17573f81a2f1 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h @@ -67,6 +67,7 @@ #define REG_SPS0_CTRL 0x0011 #define REG_SPS_OCP_CFG 0x0018 #define REG_8192E_LDOV12_CTRL 0x0014 +#define REG_SYS_SWR_CTRL2 0x0014 #define REG_RSV_CTRL 0x001c #define RSV_CTRL_WLOCK_1C BIT(5) #define RSV_CTRL_DIS_PRST BIT(6) @@ -215,6 +216,8 @@ #define REG_HMBOX_EXT_2 0x008c #define REG_HMBOX_EXT_3 0x008e +#define REG_RSVD_1 0x0097 + /* Interrupt registers for 8192e/8723bu/8812 */ #define REG_HIMR0 0x00b0 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit @@ -283,6 +286,7 @@ #define REG_BIST_SCAN 0x00d0 #define REG_BIST_RPT 0x00d4 #define REG_BIST_ROM_RPT 0x00d8 +#define REG_RSVD_4 0x00dc #define REG_USB_SIE_INTF 0x00e0 #define REG_PCIE_MIO_INTF 0x00e4 #define REG_PCIE_MIO_INTD 0x00e8 @@ -390,6 +394,12 @@ #define TRXDMA_CTRL_BKQ_SHIFT 10 #define TRXDMA_CTRL_MGQ_SHIFT 12 #define TRXDMA_CTRL_HIQ_SHIFT 14 +#define TRXDMA_CTRL_VOQ_SHIFT_8192F 4 +#define TRXDMA_CTRL_VIQ_SHIFT_8192F 7 +#define TRXDMA_CTRL_BEQ_SHIFT_8192F 10 +#define TRXDMA_CTRL_BKQ_SHIFT_8192F 13 +#define TRXDMA_CTRL_MGQ_SHIFT_8192F 16 +#define TRXDMA_CTRL_HIQ_SHIFT_8192F 19 #define TRXDMA_QUEUE_LOW 1 #define TRXDMA_QUEUE_NORMAL 2 #define TRXDMA_QUEUE_HIGH 3 @@ -973,12 +983,18 @@ #define FPGA1_TX_OFDM_TXSC_MASK 0x30000000 #define REG_ANT_MAPPING1 0x0914 +#define REG_RFE_OPT 0x0920 #define REG_DPDT_CTRL 0x092c /* 8723BU */ #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ +#define REG_RFE_CTRL_ANT_SRC1 0x0934 +#define REG_RFE_CTRL_ANT_SRC2 0x0938 +#define REG_RFE_CTRL_ANT_SRC3 0x093c #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ #define REG_RFE_BUFFER 0x0944 /* 8723BU */ #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ +#define REG_RX_DFIR_MOD_97F 0x0948 #define REG_OFDM_RX_DFIR 0x954 +#define REG_RFE_OPT62 0x0968 #define REG_CCK0_SYSTEM 0x0a00 #define CCK0_SIDEBAND BIT(4) @@ -1038,6 +1054,8 @@ #define REG_OFDM0_FA_RSTC 0x0c0c +#define REG_DOWNSAM_FACTOR 0x0c10 + #define REG_OFDM0_XA_RX_AFE 0x0c10 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c @@ -1074,6 +1092,8 @@ /* 8188eu */ #define REG_ANTDIV_PARA1 0x0ca4 +#define REG_RXIQB_EXT 0x0ca8 + /* 8723bu */ #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 @@ -1093,6 +1113,8 @@ #define REG_OFDM1_CSI_FIX_MASK1 0x0d40 #define REG_OFDM1_CSI_FIX_MASK2 0x0d44 +#define REG_ANAPWR1 0x0d94 + #define REG_TX_AGC_A_RATE18_06 0x0e00 #define REG_TX_AGC_A_RATE54_24 0x0e04 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 @@ -1101,6 +1123,10 @@ #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c +#define REG_NP_ANTA 0x0e20 + +#define REG_TAP_UPD_97F 0x0e24 + #define REG_FPGA0_IQK 0x0e28 #define REG_TX_IQK_TONE_A 0x0e30 @@ -1129,19 +1155,23 @@ #define REG_RX_CCK 0x0e8c #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 +#define REG_IQK_RPT_TXA 0x0e98 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 +#define REG_IQK_RPT_RXA 0x0ea8 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 +#define REG_IQK_RPT_TXB 0x0eb8 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 +#define REG_IQK_RPT_RXB 0x0ec8 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc #define REG_RX_OFDM 0x0ed0 @@ -1152,6 +1182,12 @@ #define REG_PMPD_ANAEN 0x0eec #define REG_FW_START_ADDRESS 0x1000 +#define REG_FW_START_ADDRESS_8192F 0x4000 + +#define REG_SW_GPIO_SHARE_CTRL_0 0x1038 +#define REG_SW_GPIO_SHARE_CTRL_1 0x103c +#define REG_GPIO_A0 0x1050 +#define REG_GPIO_B0 0x105b #define REG_USB_INFO 0xfe17 #define REG_USB_HIMR 0xfe38 @@ -1316,12 +1352,15 @@ /* * NextGen regs: 8723BU */ +#define RF6052_REG_GAIN_P1 0x35 #define RF6052_REG_T_METER_8723B 0x42 #define RF6052_REG_UNKNOWN_43 0x43 #define RF6052_REG_UNKNOWN_55 0x55 #define RF6052_REG_UNKNOWN_56 0x56 +#define RF6052_REG_TXMOD 0x58 #define RF6052_REG_RXG_MIX_SWBW 0x87 #define RF6052_REG_S0S1 0xb0 #define RF6052_REG_UNKNOWN_DF 0xdf #define RF6052_REG_UNKNOWN_ED 0xed #define RF6052_REG_WE_LUT 0xef +#define RF6052_REG_GAIN_CTRL 0xf5 |