diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-11-02 02:09:46 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-11-02 02:09:46 +0300 |
commit | 3c86a44d623ee8734a02636d3544812e31496460 (patch) | |
tree | d6b1a8b40ab8d810e265644e1fe2b3c55c553a10 /drivers/pmdomain/mediatek/mt8183-pm-domains.h | |
parent | 40aa597c4a53f7269367d1b5298bd44afcdcf473 (diff) | |
parent | 9e0cceadb7a5099c637e787191a9adbf9ec424cd (diff) | |
download | linux-3c86a44d623ee8734a02636d3544812e31496460.tar.xz |
Merge tag 'pmdomain-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
- Move Kconfig files into the pmdomain subsystem
- Drop use of genpd's redundant ->opp_to_performance_state() callback
- amlogic:
- Add support for the T7 power-domains controller
- Fix mask for the second NNA mem power-domain
- bcm: Fixup ASB register read and comparison for bcm2835-power
- imx: Fix device link problem for consumers of the pgc power-domain
- mediatek: Add support for the MT8365 power domains
- qcom:
- Add support for the rpmhpds for SC8380XP power-domains
- Add support for the rpmhpds for SM8650 power-domains
- Add support for the rpmhpd clocks for SM7150
- Add support for the rpmpds for MSM8917 (families) power-domains
- starfive: Add support for the JH7110 AON PMU
* tag 'pmdomain-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (56 commits)
pmdomain: amlogic: Fix mask for the second NNA mem PD domain
pmdomain: qcom: rpmhpd: Add SC8380XP power domains
pmdomain: qcom: rpmhpd: Add SM8650 RPMh Power Domains
dt-bindings: power: rpmpd: Add SC8380XP support
dt-bindings: power: qcom,rpmhpd: Add GMXC PD index
dt-bindings: power: qcom,rpmpd: document the SM8650 RPMh Power Domains
pmdomain: imx: Make imx pgc power domain also set the fwnode
pmdomain: qcom: rpmpd: Add QM215 power domains
pmdomain: qcom: rpmpd: Add MSM8917 power domains
dt-bindings: power: rpmpd: Add MSM8917, MSM8937 and QM215
pmdomain: bcm: bcm2835-power: check if the ASB register is equal to enable
pmdomain: qcom: rpmhpd: Drop the ->opp_to_performance_state() callback
pmdomain: qcom: rpmpd: Drop the ->opp_to_performance_state() callback
pmdomain: qcom: cpr: Drop the ->opp_to_performance_state() callback
pmdomain: Use device_get_match_data()
pmdomain: ti: add missing of_node_put
pmdomain: mediatek: Add support for MT8365
pmdomain: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
pmdomain: mediatek: Add support for WAY_EN operations
pmdomain: mediatek: Unify configuration for infracfg and smi
...
Diffstat (limited to 'drivers/pmdomain/mediatek/mt8183-pm-domains.h')
-rw-r--r-- | drivers/pmdomain/mediatek/mt8183-pm-domains.h | 125 |
1 files changed, 77 insertions, 48 deletions
diff --git a/drivers/pmdomain/mediatek/mt8183-pm-domains.h b/drivers/pmdomain/mediatek/mt8183-pm-domains.h index 99de67fe5de8..c4c1b63d85b1 100644 --- a/drivers/pmdomain/mediatek/mt8183-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8183-pm-domains.h @@ -28,9 +28,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_CONN, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_MFG_ASYNC] = { @@ -79,11 +82,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_1_MFG, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MFG, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_DISP] = { @@ -94,14 +103,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_1_DISP, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_DISP, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_DISP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -115,18 +129,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_CAM, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_CAM, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR_IGN(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_CAM, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -140,18 +160,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_ISP, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, + BUS_PROT_WR_IGN(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_ISP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -165,8 +186,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, + .bp_cfg = { + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VDEC, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -180,8 +202,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, + .bp_cfg = { + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VENC, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -195,22 +218,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_VPU_TOP, MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -224,12 +249,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), @@ -244,12 +271,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), |