diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-11-02 02:09:46 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-11-02 02:09:46 +0300 |
commit | 3c86a44d623ee8734a02636d3544812e31496460 (patch) | |
tree | d6b1a8b40ab8d810e265644e1fe2b3c55c553a10 /drivers/pmdomain/mediatek/mt8195-pm-domains.h | |
parent | 40aa597c4a53f7269367d1b5298bd44afcdcf473 (diff) | |
parent | 9e0cceadb7a5099c637e787191a9adbf9ec424cd (diff) | |
download | linux-3c86a44d623ee8734a02636d3544812e31496460.tar.xz |
Merge tag 'pmdomain-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
- Move Kconfig files into the pmdomain subsystem
- Drop use of genpd's redundant ->opp_to_performance_state() callback
- amlogic:
- Add support for the T7 power-domains controller
- Fix mask for the second NNA mem power-domain
- bcm: Fixup ASB register read and comparison for bcm2835-power
- imx: Fix device link problem for consumers of the pgc power-domain
- mediatek: Add support for the MT8365 power domains
- qcom:
- Add support for the rpmhpds for SC8380XP power-domains
- Add support for the rpmhpds for SM8650 power-domains
- Add support for the rpmhpd clocks for SM7150
- Add support for the rpmpds for MSM8917 (families) power-domains
- starfive: Add support for the JH7110 AON PMU
* tag 'pmdomain-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (56 commits)
pmdomain: amlogic: Fix mask for the second NNA mem PD domain
pmdomain: qcom: rpmhpd: Add SC8380XP power domains
pmdomain: qcom: rpmhpd: Add SM8650 RPMh Power Domains
dt-bindings: power: rpmpd: Add SC8380XP support
dt-bindings: power: qcom,rpmhpd: Add GMXC PD index
dt-bindings: power: qcom,rpmpd: document the SM8650 RPMh Power Domains
pmdomain: imx: Make imx pgc power domain also set the fwnode
pmdomain: qcom: rpmpd: Add QM215 power domains
pmdomain: qcom: rpmpd: Add MSM8917 power domains
dt-bindings: power: rpmpd: Add MSM8917, MSM8937 and QM215
pmdomain: bcm: bcm2835-power: check if the ASB register is equal to enable
pmdomain: qcom: rpmhpd: Drop the ->opp_to_performance_state() callback
pmdomain: qcom: rpmpd: Drop the ->opp_to_performance_state() callback
pmdomain: qcom: cpr: Drop the ->opp_to_performance_state() callback
pmdomain: Use device_get_match_data()
pmdomain: ti: add missing of_node_put
pmdomain: mediatek: Add support for MT8365
pmdomain: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
pmdomain: mediatek: Add support for WAY_EN operations
pmdomain: mediatek: Unify configuration for infracfg and smi
...
Diffstat (limited to 'drivers/pmdomain/mediatek/mt8195-pm-domains.h')
-rw-r--r-- | drivers/pmdomain/mediatek/mt8195-pm-domains.h | 199 |
1 files changed, 126 insertions, 73 deletions
diff --git a/drivers/pmdomain/mediatek/mt8195-pm-domains.h b/drivers/pmdomain/mediatek/mt8195-pm-domains.h index d7387ea1b9c9..59aa031ae632 100644 --- a/drivers/pmdomain/mediatek/mt8195-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8195-pm-domains.h @@ -23,12 +23,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, MT8195_TOP_AXI_PROT_EN_VDNR_SET, MT8195_TOP_AXI_PROT_EN_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -42,12 +44,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, MT8195_TOP_AXI_PROT_EN_VDNR_SET, MT8195_TOP_AXI_PROT_EN_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -95,8 +99,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_ADSP, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), @@ -111,8 +116,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_AUDIO, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), @@ -136,28 +142,34 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MFG1, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_MFG1, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_1_MFG1, MT8195_TOP_AXI_PROT_EN_1_SET, MT8195_TOP_AXI_PROT_EN_1_CLR, MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MFG1_2ND, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -222,24 +234,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VPPSYS0, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -253,16 +270,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDOSYS0, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -276,16 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -299,16 +322,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -322,8 +348,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -338,8 +365,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -364,16 +392,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_WPESYS, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -387,20 +418,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC0, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -415,12 +450,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), @@ -435,12 +472,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -455,16 +494,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VENC, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -479,12 +521,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -499,12 +543,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IMG, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), @@ -529,12 +575,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IPE, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_IPE, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -549,24 +597,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_CAM, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_CAM, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_1_CAM, MT8195_TOP_AXI_PROT_EN_1_SET, MT8195_TOP_AXI_PROT_EN_1_CLR, MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_CAM, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), |