diff options
author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2013-08-31 05:23:17 +0400 |
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committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2013-12-11 13:00:00 +0400 |
commit | 97059524ba6fd6c7dc77fa97e6957501b85af3be (patch) | |
tree | f9e96d4187760a339ca91d25862ca62fa9399462 /drivers/staging/media/omap4iss/iss_csi2.c | |
parent | 11abbfd30f74f79fe78d9ff79cc3fcfa86a975c5 (diff) | |
download | linux-97059524ba6fd6c7dc77fa97e6957501b85af3be.tar.xz |
[media] v4l: omap4iss: csi: Create and use register access functions
Replace the direct readl/writel calls with helper functions.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'drivers/staging/media/omap4iss/iss_csi2.c')
-rw-r--r-- | drivers/staging/media/omap4iss/iss_csi2.c | 122 |
1 files changed, 57 insertions, 65 deletions
diff --git a/drivers/staging/media/omap4iss/iss_csi2.c b/drivers/staging/media/omap4iss/iss_csi2.c index ac5868acb489..f8d6472aa8bd 100644 --- a/drivers/staging/media/omap4iss/iss_csi2.c +++ b/drivers/staging/media/omap4iss/iss_csi2.c @@ -29,9 +29,8 @@ static void csi2_if_enable(struct iss_csi2_device *csi2, u8 enable) { struct iss_csi2_ctrl_cfg *currctrl = &csi2->ctrl; - writel((readl(csi2->regs1 + CSI2_CTRL) & ~CSI2_CTRL_IF_EN) | - (enable ? CSI2_CTRL_IF_EN : 0), - csi2->regs1 + CSI2_CTRL); + iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTRL, CSI2_CTRL_IF_EN, + enable ? CSI2_CTRL_IF_EN : 0); currctrl->if_enable = enable; } @@ -90,7 +89,7 @@ static void csi2_recv_config(struct iss_csi2_device *csi2, */ reg |= CSI2_CTRL_ENDIANNESS; - writel(reg, csi2->regs1 + CSI2_CTRL); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTRL, reg); } static const unsigned int csi2_input_fmts[] = { @@ -260,10 +259,10 @@ static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr) ctx->ping_addr = addr; ctx->pong_addr = addr; - writel(ctx->ping_addr, - csi2->regs1 + CSI2_CTX_PING_ADDR(ctx->ctxnum)); - writel(ctx->pong_addr, - csi2->regs1 + CSI2_CTX_PONG_ADDR(ctx->ctxnum)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum), + ctx->ping_addr); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum), + ctx->pong_addr); } /* @@ -288,7 +287,7 @@ static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable) struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum]; u32 reg; - reg = readl(csi2->regs1 + CSI2_CTX_CTRL1(ctxnum)); + reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum)); if (enable) { unsigned int skip = 0; @@ -306,7 +305,7 @@ static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable) reg &= ~CSI2_CTX_CTRL1_CTX_EN; } - writel(reg, csi2->regs1 + CSI2_CTX_CTRL1(ctxnum)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum), reg); ctx->enabled = enable; } @@ -330,7 +329,7 @@ static void csi2_ctx_config(struct iss_csi2_device *csi2, if (ctx->checksum_enabled) reg |= CSI2_CTX_CTRL1_CS_EN; - writel(reg, csi2->regs1 + CSI2_CTX_CTRL1(ctx->ctxnum)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg); /* Set up CSI2_CTx_CTRL2 */ reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT; @@ -342,23 +341,20 @@ static void csi2_ctx_config(struct iss_csi2_device *csi2, if (is_usr_def_mapping(ctx->format_id)) reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT; - writel(reg, csi2->regs1 + CSI2_CTX_CTRL2(ctx->ctxnum)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg); /* Set up CSI2_CTx_CTRL3 */ - writel(ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT, - csi2->regs1 + CSI2_CTX_CTRL3(ctx->ctxnum)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL3(ctx->ctxnum), + ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT); /* Set up CSI2_CTx_DAT_OFST */ - reg = readl(csi2->regs1 + CSI2_CTX_DAT_OFST(ctx->ctxnum)); - reg &= ~CSI2_CTX_DAT_OFST_MASK; - reg |= ctx->data_offset; - writel(reg, csi2->regs1 + CSI2_CTX_DAT_OFST(ctx->ctxnum)); + iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTX_DAT_OFST(ctx->ctxnum), + CSI2_CTX_DAT_OFST_MASK, ctx->data_offset); - writel(ctx->ping_addr, - csi2->regs1 + CSI2_CTX_PING_ADDR(ctx->ctxnum)); - - writel(ctx->pong_addr, - csi2->regs1 + CSI2_CTX_PONG_ADDR(ctx->ctxnum)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum), + ctx->ping_addr); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum), + ctx->pong_addr); } /* @@ -370,7 +366,7 @@ static void csi2_timing_config(struct iss_csi2_device *csi2, { u32 reg; - reg = readl(csi2->regs1 + CSI2_TIMING); + reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_TIMING); if (timing->force_rx_mode) reg |= CSI2_TIMING_FORCE_RX_MODE_IO1; @@ -391,7 +387,7 @@ static void csi2_timing_config(struct iss_csi2_device *csi2, reg |= timing->stop_state_counter << CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT; - writel(reg, csi2->regs1 + CSI2_TIMING); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_TIMING, reg); } /* @@ -407,14 +403,14 @@ static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable) reg |= CSI2_CTX_IRQ_FS; for (i = 0; i < 8; i++) { - writel(reg, csi2->regs1 + CSI2_CTX_IRQSTATUS(i)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(i), + reg); if (enable) - writel(readl(csi2->regs1 + CSI2_CTX_IRQENABLE(i)) | reg, - csi2->regs1 + CSI2_CTX_IRQENABLE(i)); + iss_reg_set(csi2->iss, csi2->regs1, + CSI2_CTX_IRQENABLE(i), reg); else - writel(readl(csi2->regs1 + CSI2_CTX_IRQENABLE(i)) & - ~reg, - csi2->regs1 + CSI2_CTX_IRQENABLE(i)); + iss_reg_clr(csi2->iss, csi2->regs1, + CSI2_CTX_IRQENABLE(i), reg); } } @@ -452,12 +448,13 @@ static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable) CSI2_COMPLEXIO_IRQ_ERRESC1 | CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 | CSI2_COMPLEXIO_IRQ_ERRSOTHS1; - writel(reg, csi2->regs1 + CSI2_COMPLEXIO_IRQSTATUS); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg); if (enable) - reg |= readl(csi2->regs1 + CSI2_COMPLEXIO_IRQENABLE); + iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE, + reg); else - reg = 0; - writel(reg, csi2->regs1 + CSI2_COMPLEXIO_IRQENABLE); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE, + 0); } /* @@ -474,13 +471,11 @@ static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable) CSI2_IRQ_COMPLEXIO_ERR | CSI2_IRQ_FIFO_OVF | CSI2_IRQ_CONTEXT0; - writel(reg, csi2->regs1 + CSI2_IRQSTATUS); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg); if (enable) - reg |= readl(csi2->regs1 + CSI2_IRQENABLE); + iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg); else - reg = 0; - - writel(reg, csi2->regs1 + CSI2_IRQENABLE); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQENABLE, 0); } /* @@ -502,13 +497,12 @@ int omap4iss_csi2_reset(struct iss_csi2_device *csi2) if (csi2->phy->phy_in_use) return -EBUSY; - writel(readl(csi2->regs1 + CSI2_SYSCONFIG) | - CSI2_SYSCONFIG_SOFT_RESET, - csi2->regs1 + CSI2_SYSCONFIG); + iss_reg_set(csi2->iss, csi2->regs1, CSI2_SYSCONFIG, + CSI2_SYSCONFIG_SOFT_RESET); do { - reg = readl(csi2->regs1 + CSI2_SYSSTATUS) & - CSI2_SYSSTATUS_RESET_DONE; + reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_SYSSTATUS) + & CSI2_SYSSTATUS_RESET_DONE; if (reg == CSI2_SYSSTATUS_RESET_DONE) break; soft_reset_retries++; @@ -522,13 +516,12 @@ int omap4iss_csi2_reset(struct iss_csi2_device *csi2) return -EBUSY; } - writel(readl(csi2->regs1 + CSI2_COMPLEXIO_CFG) | - CSI2_COMPLEXIO_CFG_RESET_CTRL, - csi2->regs1 + CSI2_COMPLEXIO_CFG); + iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_CFG, + CSI2_COMPLEXIO_CFG_RESET_CTRL); i = 100; do { - reg = readl(csi2->phy->phy_regs + REGISTER1) + reg = iss_reg_read(csi2->iss, csi2->phy->phy_regs, REGISTER1) & REGISTER1_RESET_DONE_CTRLCLK; if (reg == REGISTER1_RESET_DONE_CTRLCLK) break; @@ -541,11 +534,10 @@ int omap4iss_csi2_reset(struct iss_csi2_device *csi2) return -EBUSY; } - writel((readl(csi2->regs1 + CSI2_SYSCONFIG) & - ~(CSI2_SYSCONFIG_MSTANDBY_MODE_MASK | - CSI2_SYSCONFIG_AUTO_IDLE)) | - CSI2_SYSCONFIG_MSTANDBY_MODE_NO, - csi2->regs1 + CSI2_SYSCONFIG); + iss_reg_update(csi2->iss, csi2->regs1, CSI2_SYSCONFIG, + CSI2_SYSCONFIG_MSTANDBY_MODE_MASK | + CSI2_SYSCONFIG_AUTO_IDLE, + CSI2_SYSCONFIG_MSTANDBY_MODE_NO); return 0; } @@ -627,7 +619,7 @@ static int csi2_configure(struct iss_csi2_device *csi2) */ #define CSI2_PRINT_REGISTER(iss, regs, name)\ dev_dbg(iss->dev, "###CSI2 " #name "=0x%08x\n", \ - readl(regs + CSI2_##name)) + iss_reg_read(iss, regs, CSI2_##name)) static void csi2_print_status(struct iss_csi2_device *csi2) { @@ -695,8 +687,8 @@ static void csi2_isr_ctx(struct iss_csi2_device *csi2, unsigned int n = ctx->ctxnum; u32 status; - status = readl(csi2->regs1 + CSI2_CTX_IRQSTATUS(n)); - writel(status, csi2->regs1 + CSI2_CTX_IRQSTATUS(n)); + status = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n)); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n), status); /* Propagate frame number */ if (status & CSI2_CTX_IRQ_FS) { @@ -745,15 +737,15 @@ void omap4iss_csi2_isr(struct iss_csi2_device *csi2) if (!csi2->available) return; - csi2_irqstatus = readl(csi2->regs1 + CSI2_IRQSTATUS); - writel(csi2_irqstatus, csi2->regs1 + CSI2_IRQSTATUS); + csi2_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_IRQSTATUS); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, csi2_irqstatus); /* Failure Cases */ if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) { - cpxio1_irqstatus = readl(csi2->regs1 + - CSI2_COMPLEXIO_IRQSTATUS); - writel(cpxio1_irqstatus, - csi2->regs1 + CSI2_COMPLEXIO_IRQSTATUS); + cpxio1_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, + CSI2_COMPLEXIO_IRQSTATUS); + iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, + cpxio1_irqstatus); dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ %x\n", cpxio1_irqstatus); pipe->error = true; @@ -1319,7 +1311,7 @@ int omap4iss_csi2_init(struct iss_device *iss) csi2a->iss = iss; csi2a->available = 1; - csi2a->regs1 = iss->regs[OMAP4_ISS_MEM_CSI2_A_REGS1]; + csi2a->regs1 = OMAP4_ISS_MEM_CSI2_A_REGS1; csi2a->phy = &iss->csiphy1; csi2a->state = ISS_PIPELINE_STREAM_STOPPED; init_waitqueue_head(&csi2a->wait); @@ -1330,7 +1322,7 @@ int omap4iss_csi2_init(struct iss_device *iss) csi2b->iss = iss; csi2b->available = 1; - csi2b->regs1 = iss->regs[OMAP4_ISS_MEM_CSI2_B_REGS1]; + csi2b->regs1 = OMAP4_ISS_MEM_CSI2_B_REGS1; csi2b->phy = &iss->csiphy2; csi2b->state = ISS_PIPELINE_STREAM_STOPPED; init_waitqueue_head(&csi2b->wait); |