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authorSamuel Holland <samuel@sholland.org>2021-11-19 07:35:39 +0300
committerMaxime Ripard <maxime@cerno.tech>2021-11-23 12:29:05 +0300
commitc962f10f3931e8409f67dc52725df13e23c67d2d (patch)
treec9ff3595d6979a0c91be392283e09dfdae431f01 /include/dt-bindings/reset/sun20i-d1-r-ccu.h
parent91389c390521a02ecfb91270f5b9d7fae4312ae5 (diff)
downloadlinux-c962f10f3931e8409f67dc52725df13e23c67d2d.tar.xz
dt-bindings: clk: Add compatibles for D1 CCUs
The D1 has a CCU and a R_CCU (PRCM CCU) like most other sunxi SoCs, with 3 and 4 clock inputs, respectively. Add the compatibles and bindings. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-2-samuel@sholland.org
Diffstat (limited to 'include/dt-bindings/reset/sun20i-d1-r-ccu.h')
-rw-r--r--include/dt-bindings/reset/sun20i-d1-r-ccu.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
new file mode 100644
index 000000000000..d93d6423d283
--- /dev/null
+++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+
+#define RST_BUS_R_TIMER 0
+#define RST_BUS_R_TWD 1
+#define RST_BUS_R_PPU 2
+#define RST_BUS_R_IR_RX 3
+#define RST_BUS_R_RTC 4
+#define RST_BUS_R_CPUCFG 5
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */