diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2023-03-23 14:01:25 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-03-23 17:04:23 +0300 |
| commit | a4a3203426f4b67535d6442ddc5dca8878a0678f (patch) | |
| tree | 70b78fef7d131bdb69f1a2b7d35da325b70c085f /sound/soc/codecs/lpass-rx-macro.c | |
| parent | e38c5e80c3d293a883c6f1d553f2146ec0bda35e (diff) | |
| download | linux-a4a3203426f4b67535d6442ddc5dca8878a0678f.tar.xz | |
ASoC: codecs: lpass: fix the order or clks turn off during suspend
The order in which clocks are stopped matters as some of the clock
like NPL are derived from MCLK.
Without this patch, Dragonboard RB5 DSP would crash with below error:
qcom_q6v5_pas 17300000.remoteproc: fatal error received:
ABT_dal.c:278:ABTimeout: AHB Bus hang is detected,
Number of bus hang detected := 2 , addr0 = 0x3370000 , addr1 = 0x0!!!
Turn off fsgen first, followed by npl and then finally mclk, which is exactly
the opposite order of enable sequence.
Fixes: 1dc3459009c3 ("ASoC: codecs: lpass: register mclk after runtime pm")
Reported-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Amit Pundir <amit.pundir@linaro.org>
Link: https://lore.kernel.org/r/20230323110125.23790-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/lpass-rx-macro.c')
| -rw-r--r-- | sound/soc/codecs/lpass-rx-macro.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c index a73a7d7a1c0a..faba4237bd3d 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -3670,9 +3670,9 @@ static int __maybe_unused rx_macro_runtime_suspend(struct device *dev) regcache_cache_only(rx->regmap, true); regcache_mark_dirty(rx->regmap); - clk_disable_unprepare(rx->mclk); - clk_disable_unprepare(rx->npl); clk_disable_unprepare(rx->fsgen); + clk_disable_unprepare(rx->npl); + clk_disable_unprepare(rx->mclk); return 0; } |