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author | Thomas Zimmermann <tzimmermann@suse.de> | 2024-03-25 23:11:58 +0300 |
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committer | Thomas Zimmermann <tzimmermann@suse.de> | 2024-03-25 23:11:58 +0300 |
commit | 36a1818f5a1e50b805317ba13f827067d50f6970 (patch) | |
tree | b9414b9509bea9f006c292a46a7632ffb57d18ee /sound/soc/meson/axg-tdm-interface.c | |
parent | 2295bd846765c766701e666ed2e4b35396be25e6 (diff) | |
parent | 4cece764965020c22cff7665b18a012006359095 (diff) | |
download | linux-36a1818f5a1e50b805317ba13f827067d50f6970.tar.xz |
Merge drm/drm-fixes into drm-misc-fixes
Backmerging to get drm-misc-fixes to the state of v6.9-rc1.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Diffstat (limited to 'sound/soc/meson/axg-tdm-interface.c')
-rw-r--r-- | sound/soc/meson/axg-tdm-interface.c | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c index 1c3d433cefd2..bf708717635b 100644 --- a/sound/soc/meson/axg-tdm-interface.c +++ b/sound/soc/meson/axg-tdm-interface.c @@ -12,6 +12,9 @@ #include "axg-tdm.h" +/* Maximum bit clock frequency according the datasheets */ +#define MAX_SCLK 100000000 /* Hz */ + enum { TDM_IFACE_PAD, TDM_IFACE_LOOPBACK, @@ -130,7 +133,7 @@ static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) case SND_SOC_DAIFMT_BP_FC: case SND_SOC_DAIFMT_BC_FP: - dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n"); + dev_err(dai->dev, "only BP_FP and BC_FC are supported\n"); fallthrough; default: return -EINVAL; @@ -153,19 +156,27 @@ static int axg_tdm_iface_startup(struct snd_pcm_substream *substream, return -EINVAL; } - /* Apply component wide rate symmetry */ if (snd_soc_component_active(dai->component)) { + /* Apply component wide rate symmetry */ ret = snd_pcm_hw_constraint_single(substream->runtime, SNDRV_PCM_HW_PARAM_RATE, iface->rate); - if (ret < 0) { - dev_err(dai->dev, - "can't set iface rate constraint\n"); - return ret; - } + + } else { + /* Limit rate according to the slot number and width */ + unsigned int max_rate = + MAX_SCLK / (iface->slots * iface->slot_width); + ret = snd_pcm_hw_constraint_minmax(substream->runtime, + SNDRV_PCM_HW_PARAM_RATE, + 0, max_rate); } - return 0; + if (ret < 0) + dev_err(dai->dev, "can't set iface rate constraint\n"); + else + ret = 0; + + return ret; } static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream, @@ -264,8 +275,8 @@ static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai, srate = iface->slots * iface->slot_width * params_rate(params); if (!iface->mclk_rate) { - /* If no specific mclk is requested, default to bit clock * 4 */ - clk_set_rate(iface->mclk, 4 * srate); + /* If no specific mclk is requested, default to bit clock * 2 */ + clk_set_rate(iface->mclk, 2 * srate); } else { /* Check if we can actually get the bit clock from mclk */ if (iface->mclk_rate % srate) { |