diff options
| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2022-10-24 19:53:07 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-10-26 16:18:06 +0300 |
| commit | 38bf07805955bc16ba436c9d822df43e6b4a8fa6 (patch) | |
| tree | a5216fe0863c7dc86706fb9b7c98a708fc136b2c /sound/soc/sof/intel/hda-loader-skl.c | |
| parent | d66149dc0fc2b72f5f2d5050d529f5a7f212700d (diff) | |
| download | linux-38bf07805955bc16ba436c9d822df43e6b4a8fa6.tar.xz | |
ASoC: SOF: Intel: hda-stream: rename CL_SD_CTL registers as SD_CTL
The use of the CL prefix is misleading. HDaudio streams are used for
code loading since ApolloLake, but they are also used for regular
audio transfers.
No functionality change, pure rename.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20221024165310.246183-14-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/sof/intel/hda-loader-skl.c')
| -rw-r--r-- | sound/soc/sof/intel/hda-loader-skl.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/sound/soc/sof/intel/hda-loader-skl.c b/sound/soc/sof/intel/hda-loader-skl.c index 3211f561db29..69fdef8f89ae 100644 --- a/sound/soc/sof/intel/hda-loader-skl.c +++ b/sound/soc/sof/intel/hda-loader-skl.c @@ -141,7 +141,7 @@ static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable) u32 run = enable ? 0x1 : 0; snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL, + sd_offset + SOF_HDA_ADSP_REG_SD_CTL, HDA_CL_SD_CTL_RUN(1), HDA_CL_SD_CTL_RUN(run)); retries = 300; @@ -150,7 +150,7 @@ static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable) /* waiting for hardware to report the stream Run bit set */ val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL); + sd_offset + SOF_HDA_ADSP_REG_SD_CTL); val &= HDA_CL_SD_CTL_RUN(1); if (enable && val) break; @@ -174,23 +174,23 @@ static void cl_skl_cldma_stream_clear(struct snd_sof_dev *sdev) * Descriptor Error Interrupt and set the cldma stream number to 0. */ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL, + sd_offset + SOF_HDA_ADSP_REG_SD_CTL, HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(0)); snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL, + sd_offset + SOF_HDA_ADSP_REG_SD_CTL, HDA_CL_SD_CTL_STRM(0xf), HDA_CL_SD_CTL_STRM(0)); snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, HDA_CL_SD_BDLPLBA(0)); + sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, HDA_CL_SD_BDLPLBA(0)); snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); + sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0); /* Set the Cyclic Buffer Length to 0. */ snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, 0); + sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 0); /* Set the Last Valid Index. */ snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, 0); + sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 0); } static void cl_skl_cldma_setup_spb(struct snd_sof_dev *sdev, @@ -240,27 +240,27 @@ static void cl_skl_cldma_setup_controller(struct snd_sof_dev *sdev, /* setting the stream register */ snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, + sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, HDA_CL_SD_BDLPLBA(dmab_bdl->addr)); snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, + sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, HDA_CL_SD_BDLPUBA(dmab_bdl->addr)); /* Set the Cyclic Buffer Length. */ snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, max_size); + sd_offset + SOF_HDA_ADSP_REG_SD_CBL, max_size); /* Set the Last Valid Index. */ snd_sof_dsp_write(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, count - 1); + sd_offset + SOF_HDA_ADSP_REG_SD_LVI, count - 1); /* Set the Interrupt On Completion, FIFO Error Interrupt, * Descriptor Error Interrupt and the cldma stream number. */ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL, + sd_offset + SOF_HDA_ADSP_REG_SD_CTL, HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(1)); snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL, + sd_offset + SOF_HDA_ADSP_REG_SD_CTL, HDA_CL_SD_CTL_STRM(0xf), HDA_CL_SD_CTL_STRM(1)); } @@ -439,7 +439,7 @@ static int cl_skl_cldma_wait_interruptible(struct snd_sof_dev *sdev, /* now check DMA interrupt status */ cl_dma_intr_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, - sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS); + sd_offset + SOF_HDA_ADSP_REG_SD_STS); if (!(cl_dma_intr_status & HDA_CL_DMA_SD_INT_COMPLETE)) { dev_err(sdev->dev, "cldma copy failed\n"); |