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authorTakashi Iwai <tiwai@suse.de>2017-02-03 02:01:18 +0300
committerTakashi Iwai <tiwai@suse.de>2017-02-06 14:21:10 +0300
commite1b239f371c0c745542cb8108d085ec728e8a69c (patch)
tree5b79452798a340db7c2aabded15f4edf92465c80 /sound/x86/intel_hdmi_lpe_audio.h
parent1cf05ba2cafa079a943c2cbae51b2f2c2e247466 (diff)
downloadlinux-e1b239f371c0c745542cb8108d085ec728e8a69c.tar.xz
ALSA: x86: Refactor PCM process engine
This is again a big rewrite of the driver; now it touches the code to process PCM stream transfers. The most fundamental change is that the driver may support more than four periods. Instead of keeping the same index between both the ring buffer (with the fixed four buffer descriptors) and the PCM buffer periods, we keep difference indices for both (bd_head and pcm_head fields). In addition, when the periods are more than four, we need to track both head and next indices. That is, we now have three indices: bd_head, pcm_head and pcm_filled. Also, the driver works better for periods < 4, too: the remaining BDs out of four are marked as invalid, so that the hardware skips those BDs in its loop. By this flexibility, we can use even ALSA-lib dmix plugin, which requires 16 periods as default. The buffer size could be up to 20bit, so the max buffer size was increased accordingly. However, the buffer pre-allocation is kept as the old value (600kB) as default. The reason is the limited number of BDs: since it doesn't suffice for the useful SG page management that can fit with the usual page allocator like some other drivers, we have to still allocate continuous pages, hence we shouldn't take too big memories there. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/x86/intel_hdmi_lpe_audio.h')
-rw-r--r--sound/x86/intel_hdmi_lpe_audio.h25
1 files changed, 10 insertions, 15 deletions
diff --git a/sound/x86/intel_hdmi_lpe_audio.h b/sound/x86/intel_hdmi_lpe_audio.h
index be9783910a3a..ca4212dca94e 100644
--- a/sound/x86/intel_hdmi_lpe_audio.h
+++ b/sound/x86/intel_hdmi_lpe_audio.h
@@ -28,13 +28,13 @@
#define HAD_MAX_CHANNEL 8
#define HAD_NUM_OF_RING_BUFS 4
-/* Assume 192KHz, 8channel, 25msec period */
-#define HAD_MAX_BUFFER (600*1024)
-#define HAD_MIN_BUFFER (32*1024)
-#define HAD_MAX_PERIODS 4
-#define HAD_MIN_PERIODS 4
-#define HAD_MAX_PERIOD_BYTES (HAD_MAX_BUFFER/HAD_MIN_PERIODS)
-#define HAD_MIN_PERIOD_BYTES 256
+/* max 20bit address, aligned to 64 */
+#define HAD_MAX_BUFFER ((1024 * 1024 - 1) & ~0x3f)
+#define HAD_DEFAULT_BUFFER (600 * 1024) /* default prealloc size */
+#define HAD_MAX_PERIODS 256 /* arbitrary, but should suffice */
+#define HAD_MIN_PERIODS 2
+#define HAD_MAX_PERIOD_BYTES ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)
+#define HAD_MIN_PERIOD_BYTES 1024 /* might be smaller */
#define HAD_FIFO_SIZE 0 /* fifo not being used */
#define MAX_SPEAKERS 8
@@ -82,14 +82,6 @@
/* Naud Value */
#define DP_NAUD_VAL 32768
-/* enum intel_had_aud_buf_type - HDMI controller ring buffer types */
-enum intel_had_aud_buf_type {
- HAD_BUF_TYPE_A = 0,
- HAD_BUF_TYPE_B = 1,
- HAD_BUF_TYPE_C = 2,
- HAD_BUF_TYPE_D = 3,
-};
-
/* HDMI Controller register offsets - audio domain common */
/* Base address for below regs = 0x65000 */
enum hdmi_ctrl_reg_offset_common {
@@ -274,6 +266,9 @@ union aud_buf_addr {
u32 regval;
};
+#define AUD_BUF_VALID (1U << 0)
+#define AUD_BUF_INTR_EN (1U << 1)
+
/* Length of Audio Buffer */
union aud_buf_len {
struct {