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-rw-r--r--Documentation/devicetree/bindings/clock/fsl,plldig.yaml17
1 files changed, 8 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
index a203d5d498db..8141f22410dd 100644
--- a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
@@ -28,15 +28,14 @@ properties:
const: 0
fsl,vco-hz:
- description: Optional for VCO frequency of the PLL in Hertz.
- The VCO frequency of this PLL cannot be changed during runtime
- only at startup. Therefore, the output frequencies are very
- limited and might not even closely match the requested frequency.
- To work around this restriction the user may specify its own
- desired VCO frequency for the PLL.
- minimum: 650000000
- maximum: 1300000000
- default: 1188000000
+ description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
+ of this PLL cannot be changed during runtime only at startup. Therefore,
+ the output frequencies are very limited and might not even closely match
+ the requested frequency. To work around this restriction the user may specify
+ its own desired VCO frequency for the PLL.
+ minimum: 650000000
+ maximum: 1300000000
+ default: 1188000000
required:
- compatible