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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6375.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm6375.dtsi227
1 files changed, 179 insertions, 48 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 3dba34210a6d..e7ff55443da7 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -45,6 +46,8 @@
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -69,6 +72,8 @@
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -88,6 +93,8 @@
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -107,6 +114,8 @@
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -126,6 +135,8 @@
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -145,6 +156,8 @@
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -164,6 +177,8 @@
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -183,6 +198,8 @@
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
#cooling-cells = <2>;
@@ -300,6 +317,116 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <(300000 * 32)>;
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <(556800 * 32)>;
+ };
+
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-peak-kBps = <(652800 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(921600 * 32)>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(921600 * 32)>;
+ };
+
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(1171200 * 32)>;
+ };
+
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+ };
+
+ cpu6_opp_table: opp-table-cpu6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-peak-kBps = <(556800 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(921600 * 32)>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <(1171200 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(1382400 * 32)>;
+ };
+
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <(1497600 * 32)>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -494,67 +621,71 @@
};
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts-extended = <&ipcc IPCC_CLIENT_AOP
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ rpm: remoteproc {
+ compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc";
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-sm6375";
- qcom,glink-channels = "rpm_requests";
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
- clocks = <&xo_board_clk>;
- clock-names = "xo";
- #clock-cells = <1>;
- };
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-sm6375";
+ qcom,glink-channels = "rpm_requests";
- rpmpd: power-controller {
- compatible = "qcom,sm6375-rpmpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmpd_opp_table>;
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
- rpmpd_opp_table: opp-table {
- compatible = "operating-points-v2";
+ rpmpd: power-controller {
+ compatible = "qcom,sm6375-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
- rpmpd_opp_ret: opp1 {
- opp-level = <RPM_SMD_LEVEL_RETENTION>;
- };
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
- rpmpd_opp_min_svs: opp2 {
- opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
- };
+ rpmpd_opp_ret: opp1 {
+ opp-level = <RPM_SMD_LEVEL_RETENTION>;
+ };
- rpmpd_opp_low_svs: opp3 {
- opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
- };
+ rpmpd_opp_min_svs: opp2 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
- rpmpd_opp_svs: opp4 {
- opp-level = <RPM_SMD_LEVEL_SVS>;
- };
+ rpmpd_opp_low_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
- rpmpd_opp_svs_plus: opp5 {
- opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
- };
+ rpmpd_opp_svs: opp4 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
- rpmpd_opp_nom: opp6 {
- opp-level = <RPM_SMD_LEVEL_NOM>;
- };
+ rpmpd_opp_svs_plus: opp5 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
- rpmpd_opp_nom_plus: opp7 {
- opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
- };
+ rpmpd_opp_nom: opp6 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
- rpmpd_opp_turbo: opp8 {
- opp-level = <RPM_SMD_LEVEL_TURBO>;
- };
+ rpmpd_opp_nom_plus: opp7 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp8 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
- rpmpd_opp_turbo_no_cpr: opp9 {
- opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ rpmpd_opp_turbo_no_cpr: opp9 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
};
};
};
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-28 02:36:48 +0300