diff options
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 573 |
1 files changed, 466 insertions, 107 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index 8a4a2d161a29..7067376e25e1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h @@ -3,50 +3,28 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum vgt_event_type { VS_DEALLOC = 0, @@ -94,12 +72,14 @@ enum vgt_event_type { LRZ_FLUSH = 38, BLIT_OP_FILL_2D = 39, BLIT_OP_COPY_2D = 40, + UNK_40 = 40, BLIT_OP_SCALE_2D = 42, CONTEXT_DONE_2D = 43, UNK_2C = 44, UNK_2D = 45, CACHE_INVALIDATE = 49, LABEL = 63, + DUMMY_EVENT = 1, CCU_INVALIDATE_DEPTH = 24, CCU_INVALIDATE_COLOR = 25, CCU_RESOLVE_CLEAN = 26, @@ -192,7 +172,7 @@ enum pc_di_vis_cull_mode { }; enum adreno_pm4_packet_type { - CP_TYPE0_PKT = 0, + CP_TYPE0_PKT = 0x00000000, CP_TYPE1_PKT = 0x40000000, CP_TYPE2_PKT = 0x80000000, CP_TYPE3_PKT = 0xc0000000, @@ -224,6 +204,7 @@ enum adreno_pm4_type3_packets { CP_COND_WRITE = 69, CP_COND_WRITE5 = 69, CP_EVENT_WRITE = 70, + CP_EVENT_WRITE7 = 70, CP_EVENT_WRITE_SHD = 88, CP_EVENT_WRITE_CFL = 89, CP_EVENT_WRITE_ZPD = 91, @@ -318,6 +299,7 @@ enum adreno_pm4_type3_packets { CP_WAIT_TWO_REGS = 112, CP_MEMCPY = 117, CP_SET_BIN_DATA5_OFFSET = 46, + CP_SET_UNK_BIN_DATA = 45, CP_CONTEXT_SWITCH = 84, CP_SET_CTXSWITCH_IB = 85, CP_REG_WRITE = 109, @@ -325,13 +307,16 @@ enum adreno_pm4_type3_packets { CP_END_BIN = 81, CP_PREEMPT_DISABLE = 108, CP_WAIT_TIMESTAMP = 20, + CP_GLOBAL_TIMESTAMP = 21, + CP_LOCAL_TIMESTAMP = 22, CP_THREAD_CONTROL = 23, + CP_RESOURCE_LIST = 24, + CP_BV_BR_COUNT_OPS = 27, + CP_MODIFY_TIMESTAMP = 28, CP_CONTEXT_REG_BUNCH2 = 93, - CP_UNK15 = 21, - CP_UNK16 = 22, - CP_UNK18 = 24, - CP_UNK1B = 27, - CP_UNK49 = 73, + CP_MEM_TO_SCRATCH_MEM = 73, + CP_FIXED_STRIDE_DRAW_TABLE = 127, + CP_RESET_CONTEXT_STATE = 31, }; enum adreno_state_block { @@ -456,6 +441,13 @@ enum cp_cond_function { WRITE_GT = 6, }; +enum poll_memory_type { + POLL_REGISTER = 0, + POLL_MEMORY = 1, + POLL_SCRATCH = 2, + POLL_ON_CHIP = 3, +}; + enum render_mode_cmd { BYPASS = 1, BINNING = 2, @@ -465,6 +457,19 @@ enum render_mode_cmd { END2D = 8, }; +enum event_write_src { + EV_WRITE_USER_32B = 0, + EV_WRITE_USER_64B = 1, + EV_WRITE_TIMESTAMP_SUM = 2, + EV_WRITE_ALWAYSON = 3, + EV_WRITE_REGS_CONTENT = 4, +}; + +enum event_write_dst { + EV_DST_RAM = 0, + EV_DST_ONCHIP = 1, +}; + enum cp_blit_cmd { BLIT_OP_FILL = 0, BLIT_OP_COPY = 1, @@ -492,12 +497,31 @@ enum pseudo_reg { SECURE_SAVE_ADDR = 2, NON_PRIV_SAVE_ADDR = 3, COUNTER = 4, + DRAW_STRM_ADDRESS = 8, + DRAW_STRM_SIZE_ADDRESS = 9, + PRIM_STRM_ADDRESS = 10, + UNK_STRM_ADDRESS = 11, + UNK_STRM_SIZE_ADDRESS = 12, + BINDLESS_BASE_0_ADDR = 16, + BINDLESS_BASE_1_ADDR = 17, + BINDLESS_BASE_2_ADDR = 18, + BINDLESS_BASE_3_ADDR = 19, + BINDLESS_BASE_4_ADDR = 20, + BINDLESS_BASE_5_ADDR = 21, + BINDLESS_BASE_6_ADDR = 22, +}; + +enum source_type { + SOURCE_REG = 0, + SOURCE_SCRATCH_MEM = 1, }; enum compare_mode { PRED_TEST = 1, REG_COMPARE = 2, RENDER_MODE = 3, + REG_COMPARE_IMM = 4, + THREAD_MODE = 5, }; enum ctxswitch_ib { @@ -514,6 +538,30 @@ enum reg_tracker { TRACK_LRZ = 8, }; +enum ts_wait_value_src { + TS_WAIT_GE_32B = 0, + TS_WAIT_GE_64B = 1, + TS_WAIT_GE_TIMESTAMP_SUM = 2, +}; + +enum ts_wait_type { + TS_WAIT_RAM = 0, + TS_WAIT_ONCHIP = 1, +}; + +enum pipe_count_op { + PIPE_CLEAR_BV_BR = 1, + PIPE_SET_BR_OFFSET = 2, + PIPE_BR_WAIT_FOR_BV = 3, + PIPE_BV_WAIT_FOR_BR = 4, +}; + +enum timestamp_op { + MODIFY_TIMESTAMP_CLEAR = 0, + MODIFY_TIMESTAMP_ADD_GLOBAL = 1, + MODIFY_TIMESTAMP_ADD_LOCAL = 2, +}; + enum cp_thread { CP_SET_THREAD_BR = 1, CP_SET_THREAD_BV = 2, @@ -557,7 +605,8 @@ static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) { - return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; } #define REG_CP_LOAD_STATE4_0 0x00000000 @@ -597,7 +646,8 @@ static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) { - return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; } #define REG_CP_LOAD_STATE4_2 0x00000002 @@ -645,7 +695,8 @@ static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) { - return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; } #define REG_CP_LOAD_STATE6_2 0x00000002 @@ -834,37 +885,36 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK; } - -#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004 +#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) { - return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; + return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; } -#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 -#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005 +#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) { - return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; + return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; } -#define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 +#define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 -#define REG_CP_DRAW_INDX_OFFSET_6 0x00000006 -#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006 +#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) { - return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; + return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; } #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) +static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val) { return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; } @@ -911,7 +961,6 @@ static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type v #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 - #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 @@ -920,7 +969,6 @@ static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; } - #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 @@ -973,7 +1021,6 @@ static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_t #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 - #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 @@ -998,7 +1045,6 @@ static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; } - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 @@ -1093,37 +1139,93 @@ static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002 +#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 +#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 -#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 -#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006 +#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 -#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008 +#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005 +#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 -#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008 -#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a -#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005 +#define REG_CP_DRAW_AUTO_0 0x00000000 +#define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f +#define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val) +{ + return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK; +} +#define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0 +#define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6 +static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val) +{ + return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK; +} +#define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300 +#define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8 +static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val) +{ + return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK; +} +#define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00 +#define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10 +static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val) +{ + return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK; +} +#define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000 +#define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12 +static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val) +{ + return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK; +} +#define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000 +#define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006 +#define REG_CP_DRAW_AUTO_1 0x00000001 +#define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff +#define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val) +{ + return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK; +} -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008 +#define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002 -#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a +#define REG_CP_DRAW_AUTO_4 0x00000004 +#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff +#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val) +{ + return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK; +} + +#define REG_CP_DRAW_AUTO_5 0x00000005 +#define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff +#define CP_DRAW_AUTO_5_STRIDE__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val) +{ + return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK; +} #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001 @@ -1147,7 +1249,7 @@ static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) #define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001 -static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } +#define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*(i0)) static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff @@ -1693,8 +1795,12 @@ static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; } #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008 -#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010 -#define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020 +#define CP_COND_WRITE5_0_POLL__MASK 0x00000030 +#define CP_COND_WRITE5_0_POLL__SHIFT 4 +static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val) +{ + return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK; +} #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 #define REG_CP_COND_WRITE5_1 0x00000001 @@ -1793,8 +1899,12 @@ static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK; } #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008 -#define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010 -#define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020 +#define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030 +#define CP_WAIT_REG_MEM_0_POLL__SHIFT 4 +static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val) +{ + return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK; +} #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100 #define REG_CP_WAIT_REG_MEM_1 0x00000001 @@ -1960,14 +2070,14 @@ static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 -#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; -} #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 +#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff +#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0 +static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val) +{ + return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK; +} #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff @@ -2033,6 +2143,90 @@ static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) #define REG_CP_EVENT_WRITE_3 0x00000003 +#define REG_CP_EVENT_WRITE7_0 0x00000000 +#define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff +#define CP_EVENT_WRITE7_0_EVENT__SHIFT 0 +static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val) +{ + return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK; +} +#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000 +#define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000 +#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF 0x00004000 +#define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000 +#define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000 +#define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000 +#define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000 +#define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000 +#define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20 +static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val) +{ + return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK; +} +#define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000 +#define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24 +static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val) +{ + return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK; +} +#define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000 + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001 +#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK; +} + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002 +#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK; +} + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003 +#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; +} + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004 +#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; +} + +#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001 +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0 +static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val) +{ + return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK; +} + +#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003 +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 +static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) +{ + return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; +} + +#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004 +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 +static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) +{ + return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; +} + #define REG_CP_BLIT_0 0x00000000 #define CP_BLIT_0_OP__MASK 0x0000000f #define CP_BLIT_0_OP__SHIFT 0 @@ -2125,7 +2319,6 @@ static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 - #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 @@ -2154,7 +2347,6 @@ static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; } - #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 @@ -2205,10 +2397,10 @@ static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val) return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK; } -static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } +#define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*(i0)) static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } -#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007 +#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) { @@ -2238,6 +2430,18 @@ static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val) { return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK; } +#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff +#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0 +static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val) +{ + return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK; +} +#define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000 +#define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18 +static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val) +{ + return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK; +} #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 #define A6XX_CP_REG_TEST_0_BIT__SHIFT 20 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val) @@ -2270,9 +2474,14 @@ static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val) { return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK; } +#define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000 +#define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000 #define CP_COND_REG_EXEC_0_BINNING 0x02000000 #define CP_COND_REG_EXEC_0_GMEM 0x04000000 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000 +#define CP_COND_REG_EXEC_0_BV 0x02000000 +#define CP_COND_REG_EXEC_0_BR 0x04000000 +#define CP_COND_REG_EXEC_0_LPAC 0x08000000 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000 #define CP_COND_REG_EXEC_0_MODE__SHIFT 28 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) @@ -2280,12 +2489,53 @@ static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK; } -#define REG_CP_COND_REG_EXEC_1 0x00000001 -#define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff -#define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 -static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +#define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001 +#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff +#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 +static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +{ + return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK; +} + +#define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001 +#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff +#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0 +static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val) { - return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK; + return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK; +} +#define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000 + +#define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001 +#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff +#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 +static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +{ + return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; +} + +#define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001 +#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff +#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0 +static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val) +{ + return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK; +} + +#define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001 +#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff +#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 +static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +{ + return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; +} + +#define REG_CP_COND_REG_EXEC_2 0x00000002 +#define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff +#define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0 +static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val) +{ + return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK; } #define REG_CP_COND_EXEC_0 0x00000000 @@ -2425,10 +2675,88 @@ static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) #define REG_CP_START_BIN_BODY_DWORDS 0x00000004 #define REG_CP_WAIT_TIMESTAMP_0 0x00000000 +#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003 +#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0 +static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val) +{ + return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK; +} +#define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010 +#define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4 +static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val) +{ + return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK; +} + +#define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001 -#define REG_CP_WAIT_TIMESTAMP_ADDR 0x00000001 +#define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001 -#define REG_CP_WAIT_TIMESTAMP_TIMESTAMP 0x00000003 +#define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003 + +#define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004 + +#define REG_CP_BV_BR_COUNT_OPS_0 0x00000000 +#define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f +#define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0 +static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val) +{ + return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK; +} + +#define REG_CP_BV_BR_COUNT_OPS_1 0x00000001 +#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff +#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0 +static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val) +{ + return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK; +} + +#define REG_CP_MODIFY_TIMESTAMP_0 0x00000000 +#define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff +#define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0 +static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val) +{ + return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK; +} +#define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000 +#define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28 +static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val) +{ + return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000 +#define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f +#define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001 +#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f +#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002 +#define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff +#define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003 +#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff +#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK; +} #define REG_CP_THREAD_CONTROL_0 0x00000000 #define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003 @@ -2440,5 +2768,36 @@ static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val) #define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000 #define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000 +#define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000 + +#define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002 +#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff +#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0 +static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val) +{ + return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK; +} +#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000 +#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20 +static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val) +{ + return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK; +} + +#define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003 +#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff +#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0 +static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val) +{ + return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK; +} + +#define REG_CP_RESET_CONTEXT_STATE_0 0x00000000 +#define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001 +#define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002 +#define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004 + +#ifdef __cplusplus +#endif #endif /* ADRENO_PM4_XML */ |