index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
arch
/
arm
/
include
/
asm
/
arch_gicv3.h
Age
Commit message (
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Author
Files
Lines
2019-06-19
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
Thomas Gleixner
1
-12
/
+1
2019-03-16
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Linus Torvalds
1
-2
/
+2
2019-02-20
KVM: arm64: Fix ICH_ELRSR_EL2 sysreg naming
Marc Zyngier
1
-2
/
+2
2019-02-06
irqchip/gic-v3: Switch to PMR masking before calling IRQ handler
Julien Thierry
1
-0
/
+17
2019-02-06
arm/arm64: gic-v3: Add PMR and RPR accessors
Julien Thierry
1
-0
/
+16
2018-03-22
irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn
Marc Zyngier
1
-5
/
+1
2018-03-14
irqchip/gic-v3: Reset APgRn registers at boot time
Marc Zyngier
1
-10
/
+31
2017-10-19
irqchip/gic-v3: Add support for Range Selector (RS) feature
Shanker Donthineni
1
-0
/
+5
2017-08-31
irqchip/gic-v3-its: Add VPE interrupt masking
Marc Zyngier
1
-0
/
+6
2017-08-31
irqchip/gic-v3-its: Add VPENDBASER/VPROPBASER accessors
Marc Zyngier
1
-0
/
+28
2016-11-29
ARM: gic-v3-its: Add 32bit support to GICv3 ITS
Vladimir Murzin
1
-7
/
+47
2016-10-06
Merge tag 'kvm-4.9-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Linus Torvalds
1
-17
/
+76
2016-09-23
ARM: gic-v3: Work around definition of gic_write_bpr1
Marc Zyngier
1
-0
/
+9
2016-09-22
ARM: gic-v3: Introduce 32-to-64-bit mappings for GICv3 cpu registers
Vladimir Murzin
1
-0
/
+64
2016-09-22
ARM: Move system register accessors to asm/cp15.h
Vladimir Murzin
1
-16
/
+11
2016-09-12
irqchip/gic-v3: Reset BPR during initialization
Daniel Thompson
1
-0
/
+6
2016-02-18
irqchip/gic-v3: Add missing barrier to 32bit version of gic_read_iar()
Marc Zyngier
1
-0
/
+1
2015-12-10
irqchip/gic-v3: Add missing include for barrier.h
Marc Zyngier
1
-0
/
+1
2015-10-10
ARM: add 32bit support to GICv3
Jean-Philippe Brucker
1
-0
/
+188