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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
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visionfive-5.18.y
visionfive-5.19.y
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visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
arm
/
mm
/
proc-v7-2level.S
Age
Commit message (
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Author
Files
Lines
2022-11-08
ARM: 9263/1: use .arch directives instead of assembler command line flags
Nick Desaulniers
1
-0
/
+2
2019-06-19
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Thomas Gleixner
1
-4
/
+1
2018-05-31
ARM: spectre-v2: harden branch predictor on context switches
Russell King
1
-6
/
+0
2015-06-12
Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-next
Russell King
1
-5
/
+7
2015-06-02
ARM: redo TTBR setup code for LPAE
Russell King
1
-3
/
+3
2015-05-08
ARM: 8353/1: mm: Fix Cortex-A8 erratum 430973 segfaults for bootloaders and m...
Tony Lindgren
1
-2
/
+4
2015-04-15
ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUs
Russell King
1
-4
/
+8
2014-07-18
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
Russell King
1
-2
/
+2
2014-02-10
ARM: 7954/1: mm: remove remaining domain support from ARMv6
Will Deacon
1
-7
/
+0
2013-07-22
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2
Will Deacon
1
-1
/
+1
2013-07-15
arm: delete __cpuinit/__CPUINIT usage from all ARM users
Paul Gortmaker
1
-4
/
+0
2013-04-03
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead
Will Deacon
1
-1
/
+2
2013-02-16
ARM: 7650/1: mm: replace direct access to mm->context.id with new macro
Ben Dooks
1
-1
/
+1
2012-11-09
ARM: mm: introduce present, faulting entries for PAGE_NONE
Will Deacon
1
-0
/
+4
2012-11-09
ARM: mm: introduce L_PTE_VALID for page table entries
Will Deacon
1
-1
/
+1
2012-11-09
ARM: mm: don't use the access flag permissions mechanism for classic MMU
Will Deacon
1
-2
/
+2
2012-07-09
ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process
Will Deacon
1
-0
/
+5
2012-04-17
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs
Catalin Marinas
1
-3
/
+0
2012-04-17
ARM: Use TTBR1 instead of reserved context ID
Will Deacon
1
-6
/
+4
2011-12-08
ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S
Catalin Marinas
1
-0
/
+171