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2024-05-28arm64: dts: allwinner: Fix PMIC interrupt numberAndre Przywara1-1/+1
The "r_intc" interrupt controller on the A64 uses a mapping scheme, so the first (and only) NMI interrupt #0 appears as interrupt number 32 (cf. the top comment in drivers/irqchip/irq-sun6i-r.c). Fix that number in the interrupts property to properly forward PMIC interrupts to the CPU. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Fixes: 4d39a8eb07eb ("arm64: dts: allwinner: Add Jide Remix Mini PC support") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20240515234852.26929-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-04-16arm64: dts: allwinner: drop underscore in node namesKrzysztof Kozlowski1-1/+1
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for pwrseq node, because generic naming is favored by Devicetree spec. All the clocks affected by this change use clock-output-names, so resulting clock name should not change. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240317184130.157695-2-krzysztof.kozlowski@linaro.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-02-23arm64: dts: allwinner: Add Jide Remix Mini PC supportAndre Przywara1-0/+356
The Remix Mini PC is a "mini computer" using the Allwinner H64 SoC, which appears to be just a relabelled A64. It was launched in 2015 by the now defunct company Jide, and shipped with a desktop optimised version of Android. It features - Allwinner H64 Soc (4 * Arm Cortex-A53 cores) - 1 or 2 GB DRAM - 8 or 16 GB eMMC flash - 100 MBit Ethernet port (using an X-Powers AC200 PHY) - RTL8723BS WiFi & Bluetooth chip - HDMI port - two USB 2.0 ports - 3.5mm AV port - microSD card slot The devicetree covers most peripherals, though there is no agreed binding for the PHY chip yet, so this is left out. The eMMC did not work with the MMC DDR speed mode, so this mode property is omitted. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240209114018.3580370-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>