summaryrefslogtreecommitdiff
path: root/arch/mips/kernel/octeon_switch.S
AgeCommit message (Expand)AuthorFilesLines
2015-10-02MIPS: Fix octeon FP context switch handlingPaul Burton1-25/+1
2015-02-20MIPS: OCTEON: Delete unused COP2 saving codeAleksey Makarov1-26/+0
2015-02-20MIPS: OCTEON: Use correct instruction to read 64-bit COP0 registerChandrakala Chavva1-3/+3
2015-02-20MIPS: OCTEON: Save and restore CP2 SHA3 stateDavid Daney1-11/+32
2015-02-20MIPS: OCTEON: Fix FP context save.David Daney1-12/+7
2015-02-20MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUsDavid Daney1-30/+98
2014-05-30MIPS: OCTEON: Enable use of FPUDavid Daney1-23/+61
2013-10-07MIPS: stack protector: Fix per-task canary switchJames Hogan1-1/+1
2013-07-01MIPS: r4k,octeon,r2300: stack protector: change canary per taskGregory Fong1-0/+7
2013-06-13MIPS: Move cop2 save/restore to switch_to()Jayachandran C1-27/+0
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-52/+52
2012-12-28MIPS: Don't include <asm/page.h> unnecessarily.Ralf Baechle1-1/+0
2012-07-19MIPS: Fix race condition with FPU thread task flag during context switch.Leonid Yegoshin1-1/+1
2011-04-06update David Miller's old email addressJustin P. Mattock1-1/+1
2010-02-27MIPS: Nuke trailing blank linesRalf Baechle1-1/+0
2009-09-17MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.Ralf Baechle1-3/+0
2009-01-11MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney1-0/+506