index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
riscv
/
include
/
asm
/
alternative.h
Age
Commit message (
Expand
)
Author
Files
Lines
2023-09-08
Merge patch series "Add non-coherent DMA support for AX45MP"
Palmer Dabbelt
1
-0
/
+3
2023-09-01
riscv: errata: Add Andes alternative ports
Lad Prabhakar
1
-0
/
+3
2023-09-01
RISC-V: alternative: Remove feature_probe_func
Evan Green
1
-5
/
+0
2023-04-26
RISC-V: hwprobe: Remove __init on probe_vendor_features()
Evan Green
1
-1
/
+1
2023-04-19
Merge patch series "RISC-V Hardware Probing User Interface"
Palmer Dabbelt
1
-0
/
+5
2023-04-19
RISC-V: hwprobe: Support probing of misaligned access performance
Evan Green
1
-0
/
+5
2023-03-15
RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work
Andrew Jones
1
-0
/
+4
2023-03-15
riscv: alternatives: Rename errata_id to patch_id
Andrew Jones
1
-2
/
+2
2023-03-15
riscv: alternatives: Remove unnecessary define and unused struct
Andrew Jones
1
-7
/
+0
2023-02-01
riscv: switch to relative alternative entries
Jisheng Zhang
1
-6
/
+11
2022-12-29
RISC-V: fix auipc-jalr addresses in patched alternatives
Heiko Stuebner
1
-0
/
+3
2022-05-12
riscv: add memory-type errata for T-Head
Heiko Stuebner
1
-0
/
+6
2022-05-12
riscv: add RISC-V Svpbmt extension support
Heiko Stuebner
1
-0
/
+3
2022-05-12
riscv: implement module alternatives
Heiko Stuebner
1
-0
/
+3
2022-05-12
riscv: allow different stages with alternatives
Heiko Stuebner
1
-1
/
+4
2022-05-12
riscv: integrate alternatives better into the main architecture
Heiko Stuebner
1
-0
/
+8
2021-04-26
riscv: sifive: Add SiFive alternative ports
Vincent Chen
1
-0
/
+3
2021-04-26
riscv: Introduce alternative mechanism to apply errata solution
Vincent Chen
1
-0
/
+36