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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
/
riscv
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include
/
asm
/
csr.h
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Commit message (
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Author
Files
Lines
2022-03-22
perf: RISC-V: Add support for SBI PMU and Sscofpmf
Palmer Dabbelt
1
-1
/
+65
2022-03-22
RISC-V: Add sscofpmf extension support
Atish Patra
1
-1
/
+7
2022-03-22
RISC-V: Add CSR encodings for all HPMCOUNTERS
Atish Patra
1
-0
/
+58
2022-02-15
riscv: mm: Set sv57 on defaultly
Qinglin Pan
1
-0
/
+1
2022-01-20
riscv: Implement sv48 support
Alexandre Ghiti
1
-2
/
+1
2021-10-04
RISC-V: Add hypervisor extension related CSR defines
Anup Patel
1
-0
/
+87
2021-04-26
riscv: Introduce alternative mechanism to apply errata solution
Vincent Chen
1
-0
/
+3
2021-02-19
RISC-V: Implement ASID allocator
Anup Patel
1
-0
/
+6
2020-05-05
RISC-V: Remove N-extension related defines
Anup Patel
1
-3
/
+0
2020-02-18
riscv: set pmp configuration if kernel is running in M-mode
Greentime Hu
1
-0
/
+12
2020-01-05
riscv: prefix IRQ_ macro names with an RV_ namespace
Paul Walmsley
1
-9
/
+9
2019-11-18
riscv: clear the instruction cache and all registers when booting
Christoph Hellwig
1
-0
/
+1
2019-11-18
riscv: read the hart ID from mhartid on boot
Damien Le Moal
1
-0
/
+1
2019-11-05
riscv: abstract out CSR names for supervisor vs machine mode
Christoph Hellwig
1
-10
/
+62
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
1
-9
/
+1
2019-05-17
RISC-V: Access CSRs using CSR numbers
Anup Patel
1
-7
/
+25
2019-05-17
RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
Anup Patel
1
-4
/
+17
2019-05-17
RISC-V: Use tabs to align macro values in asm/csr.h
Anup Patel
1
-38
/
+38
2018-08-13
RISC-V: add a definition for the SIE SEIE bit
Christoph Hellwig
1
-0
/
+1
2018-01-31
riscv: rename sptbr to satp
Christoph Hellwig
1
-7
/
+7
2018-01-08
riscv: rename SR_* constants to match the spec
Christoph Hellwig
1
-4
/
+4
2017-09-27
RISC-V: Generic library routines and assembly
Palmer Dabbelt
1
-0
/
+132