index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
riscv
/
include
/
asm
/
timex.h
Age
Commit message (
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)
Author
Files
Lines
2023-06-10
init: consolidate prototypes in linux/init.h
Arnd Bergmann
1
-2
/
+0
2022-05-14
riscv: use fallback for random_get_entropy() instead of zero
Jason A. Donenfeld
1
-1
/
+1
2021-03-10
riscv: time: Fix no prototype for time_init
Nanyong Sun
1
-0
/
+2
2020-12-11
RISC-V: Define get_cycles64() regardless of M-mode
Palmer Dabbelt
1
-2
/
+2
2020-09-30
RISC-V: Check clint_time_val before use
Anup Patel
1
-0
/
+13
2020-09-19
RISC-V: Resurrect the MMIO timer implementation for M-mode systems
Palmer Dabbelt
1
-0
/
+27
2020-08-20
RISC-V: Remove CLINT related code from timer and arch
Anup Patel
1
-21
/
+7
2019-11-14
riscv: add support for MMIO access to the timer registers
Christoph Hellwig
1
-2
/
+17
2019-09-05
riscv: don't use the rdtime(h) pseudo-instructions
Christoph Hellwig
1
-23
/
+21
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
1
-9
/
+1
2017-11-30
RISC-V: Use define for get_cycles like other architectures
Olof Johansson
1
-1
/
+2
2017-09-27
RISC-V: Device, timer, IRQs, and the SBI
Palmer Dabbelt
1
-0
/
+59