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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
riscv
/
kernel
/
cpufeature.c
Age
Commit message (
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Author
Files
Lines
2024-01-10
Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"
Palmer Dabbelt
1
-0
/
+2
2024-01-10
riscv: add ISA extension parsing for Zacas
Clément Léger
1
-0
/
+1
2024-01-10
riscv: add ISA extension parsing for Ztso
Clément Léger
1
-0
/
+1
2024-01-03
RISC-V: Remove the removed single-letter extensions
Palmer Dabbelt
1
-4
/
+0
2023-12-13
riscv: add ISA extension parsing for Zfa
Clément Léger
1
-0
/
+1
2023-12-13
riscv: add ISA extension parsing for Zvfh[min]
Clément Léger
1
-0
/
+2
2023-12-13
riscv: add ISA extension parsing for Zihintntl
Clément Léger
1
-0
/
+1
2023-12-13
riscv: add ISA extension parsing for Zfh/Zfh[min]
Clément Léger
1
-0
/
+2
2023-12-13
riscv: add ISA extension parsing for vector crypto
Clément Léger
1
-0
/
+64
2023-12-13
riscv: add ISA extension parsing for scalar crypto
Evan Green
1
-23
/
+95
2023-12-13
riscv: add ISA extension parsing for Zbc
Clément Léger
1
-0
/
+1
2023-11-10
Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
1
-13
/
+79
2023-11-08
Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
1
-5
/
+12
2023-11-08
RISC-V: Probe misaligned access speed in parallel
Evan Green
1
-19
/
+77
2023-11-05
riscv: don't probe unaligned access speed if already done
Jisheng Zhang
1
-0
/
+4
2023-11-05
Merge patch series "Add support to handle misaligned accesses in S-mode"
Palmer Dabbelt
1
-1
/
+5
2023-11-01
riscv: report misaligned accesses emulation to hwprobe
Clément Léger
1
-0
/
+4
2023-11-01
riscv: annotate check_unaligned_access_boot_cpu() with __init
Clément Léger
1
-1
/
+1
2023-11-01
RISC-V: clarify the QEMU workaround in ISA parser
Tsukasa OI
1
-3
/
+4
2023-10-12
RISC-V: Detect Zicond from ISA string
Anup Patel
1
-0
/
+1
2023-10-12
RISC-V: Detect Smstateen extension
Mayuresh Chitale
1
-0
/
+1
2023-09-21
RISC-V: Enable cbo.zero in usermode
Andrew Jones
1
-0
/
+6
2023-09-21
RISC-V: Make zicbom/zicboz errors consistent
Andrew Jones
1
-2
/
+2
2023-09-08
Merge patch series "RISC-V: Probe for misaligned access speed"
Palmer Dabbelt
1
-0
/
+104
2023-09-01
RISC-V: Probe for unaligned access speed
Evan Green
1
-0
/
+104
2023-09-01
Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
1
-181
/
+340
2023-08-31
Merge tag 'devicetree-header-cleanups-for-6.6' of git://git.kernel.org/pub/sc...
Linus Torvalds
1
-1
/
+0
2023-08-28
riscv: Explicitly include correct DT includes
Rob Herring
1
-1
/
+0
2023-07-26
RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"
Conor Dooley
1
-1
/
+13
2023-07-26
RISC-V: enable extension detection from dedicated properties
Conor Dooley
1
-4
/
+74
2023-07-26
RISC-V: split riscv_fill_hwcap() in 3
Conor Dooley
1
-168
/
+177
2023-07-26
RISC-V: add single letter extensions to riscv_isa_ext
Conor Dooley
1
-0
/
+13
2023-07-26
RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()
Conor Dooley
1
-21
/
+9
2023-07-26
RISC-V: shunt isa_ext_arr to cpufeature.c
Conor Dooley
1
-0
/
+67
2023-07-12
RISC-V: Don't include Zicsr or Zifencei in I from ACPI
Palmer Dabbelt
1
-7
/
+2
2023-06-23
Merge patch series "ISA string parser cleanups"
Palmer Dabbelt
1
-23
/
+85
2023-06-21
RISC-V: always report presence of extensions formerly part of the base ISA
Conor Dooley
1
-0
/
+17
2023-06-21
RISC-V: remove decrement/increment dance in ISA string parser
Conor Dooley
1
-8
/
+6
2023-06-21
RISC-V: rework comments in ISA string parser
Conor Dooley
1
-11
/
+59
2023-06-21
RISC-V: validate riscv,isa at boot, not during ISA string parsing
Conor Dooley
1
-6
/
+6
2023-06-21
RISC-V: simplify register width check in ISA string parsing
Conor Dooley
1
-8
/
+7
2023-06-20
Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"
Palmer Dabbelt
1
-6
/
+10
2023-06-19
RISC-V: Track ISA extensions per hart
Evan Green
1
-6
/
+12
2023-06-19
RISC-V: Add Zba, Zbs extension probing
Evan Green
1
-0
/
+2
2023-06-14
riscv: say disabling zicbom if no or bad riscv,cbom-block-size found
Ben Dooks
1
-2
/
+2
2023-06-08
Merge patch series "riscv: Add vector ISA support"
Palmer Dabbelt
1
-0
/
+25
2023-06-08
riscv: Add prctl controls for userspace vector management
Andy Chiu
1
-1
/
+8
2023-06-08
riscv: hwcap: change ELF_HWCAP to a function
Andy Chiu
1
-0
/
+5
2023-06-08
riscv: Introduce riscv_v_vsize to record size of Vector context
Greentime Hu
1
-0
/
+2
2023-06-08
riscv: Extending cpufeature.c to detect V-extension
Guo Ren
1
-0
/
+11
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