starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-05-22	Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds	1	-54/+21
2024-04-29	riscv: mm: Always use an ASID to flush mm contexts	Samuel Holland	1	-2/+1
2024-04-29	riscv: mm: Introduce cntx2asid/cntx2version helper macros	Samuel Holland	1	-1/+1
2024-04-29	riscv: Avoid TLB flush loops when affected by SiFive CIP-1200	Samuel Holland	1	-1/+1
2024-04-29	riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma	Samuel Holland	1	-23/+0
2024-04-29	riscv: Only send remote fences when some other CPU is online	Samuel Holland	1	-1/+3
2024-04-29	riscv: mm: Broadcast kernel TLB flushes only when needed	Samuel Holland	1	-13/+5
2024-04-29	riscv: Use IPIs for remote cache/TLB flushes by default	Samuel Holland	1	-17/+14
2024-03-26	riscv: mm: Fix prototype to avoid discarding const	Samuel Holland	1	-2/+2
2024-02-07	riscv: Fix arch_tlbbatch_flush() by clearing the batch cpumask	Alexandre Ghiti	1	-0/+1
2024-01-31	riscv: mm: execute local TLB flush after populating vmemmap	Vincent Chen	1	-1/+2
2024-01-20	Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-20/+49
2024-01-11	riscv: Add support for BATCHED_UNMAP_TLB_FLUSH	Alexandre Ghiti	1	-20/+49
2023-12-14	mm: Introduce flush_cache_vmap_early()	Alexandre Ghiti	1	-0/+5
2023-11-06	riscv: Improve flush_tlb_kernel_range()	Alexandre Ghiti	1	-10/+24
2023-11-06	riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb	Alexandre Ghiti	1	-56/+59
2023-11-06	riscv: Improve flush_tlb_range() for hugetlb pages	Alexandre Ghiti	1	-1/+28
2023-11-06	riscv: Improve tlb_flush()	Alexandre Ghiti	1	-0/+7
2023-04-08	RISC-V: Use IPIs for remote TLB flush when possible	Anup Patel	1	-15/+78
2023-03-22	riscv: mm: Fix incorrect ASID argument when flushing TLB	Dylan Jhong	1	-1/+1
2023-03-10	Revert "riscv: mm: notify remote harts about mmu cache updates"	Sergey Matyukevich	1	-11/+17
2022-12-09	riscv: mm: notify remote harts about mmu cache updates	Sergey Matyukevich	1	-17/+11
2022-01-20	RISC-V: Do not use cpumask data structure for hartid bitmap	Atish Patra	1	-7/+2
2021-07-01	riscv: add ASID-based tlbflushing methods	Guo Ren	1	-7/+40
2021-07-01	riscv: pass the mm_struct to __sbi_tlb_flush_range	Christoph Hellwig	1	-9/+6
2021-05-22	riscv: mm: add THP support on 64-bit	Nanyong Sun	1	-0/+7
2021-05-22	riscv: mm: add param stride for __sbi_tlb_flush_range	Nanyong Sun	1	-5/+5
2019-10-29	RISC-V: Issue a tlb page flush if possible	Atish Patra	1	-1/+4
2019-10-29	RISC-V: Issue a local tlbflush if possible.	Atish Patra	1	-2/+17
2019-10-29	RISC-V: Do not invoke SBI call if cpumask is empty	Atish Patra	1	-0/+3
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	1	-0/+35