index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
xtensa
/
boot
/
dts
/
xtfpga.dtsi
Age
Commit message (
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)
Author
Files
Lines
2017-11-02
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Greg Kroah-Hartman
1
-0
/
+1
2016-09-21
xtensa: rearrange CCOUNT calibration
Max Filippov
1
-3
/
+1
2016-09-21
xtensa: xtfpga: use clock provider, don't update DT
Max Filippov
1
-5
/
+6
2016-03-11
xtensa: xtfpga: fix earlycon endianness
Max Filippov
1
-1
/
+1
2016-03-11
xtensa: xtfpga: fix i2c controller register width and endianness
Max Filippov
1
-1
/
+2
2016-03-11
xtensa: xtfpga: fix ethernet controller endianness
Max Filippov
1
-0
/
+1
2016-03-11
xtensa: xtfpga: fix serial port register width and endianness
Max Filippov
1
-0
/
+2
2015-02-07
xtensa: xtfpga: add audio card to xtfpga DTS
Max Filippov
1
-0
/
+64
2014-04-06
xtensa: xtfpga: introduce SoC I/O bus
Max Filippov
1
-15
/
+22
2014-02-21
xtensa: xtfpga: set ethoc clock frequency
Max Filippov
1
-0
/
+1
2014-02-21
xtensa: xtfpga: use common clock framework
Max Filippov
1
-3
/
+8
2014-01-15
xtensa: standardize devicetree cpu compatible strings
Baruch Siach
1
-2
/
+2
2014-01-14
xtensa: move built-in PIC to drivers/irqchip
Max Filippov
1
-1
/
+1
2012-12-19
xtensa: add XTFPGA DTS
Max Filippov
1
-0
/
+56