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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
at91
/
clk-pll.c
Age
Commit message (
Expand
)
Author
Files
Lines
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Thomas Gleixner
1
-6
/
+1
2018-10-19
Merge branches 'clk-actions-reset', 'clk-imx7-init-critical', 'clk-mmp2-ids' ...
Stephen Boyd
1
-182
/
+5
2018-10-17
clk: at91: move DT compatibility code to its own file
Alexandre Belloni
1
-163
/
+0
2018-10-17
clk: at91: allow clock registration from C code
Alexandre Belloni
1
-19
/
+5
2018-10-17
clk: at91: Fix division by zero in PLL recalc_rate()
Ronald Wahl
1
-0
/
+3
2018-05-16
clk: at91: PLL recalc_rate() now using cached MUL and DIV values
Marcin Ziemianowicz
1
-12
/
+1
2017-04-22
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
Markus Elfring
1
-3
/
+3
2016-09-15
clk: at91: Migrate to clk_hw based registration and OF APIs
Stephen Boyd
1
-9
/
+12
2016-02-17
clk: at91: remove IRQ handling and use polling
Alexandre Belloni
1
-43
/
+4
2016-02-17
clk: at91: make use of syscon/regmap internally
Boris Brezillon
1
-49
/
+70
2015-07-11
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...
Linus Torvalds
1
-2
/
+6
2015-07-02
clk: at91: do not leak resources
David Dueck
1
-2
/
+6
2015-06-19
clk: at91: pll: fix input range validity check
Boris Brezillon
1
-2
/
+10
2014-09-03
clk: at91: fix recalc_rate implementation of PLL driver
Boris BREZILLON
1
-8
/
+3
2014-09-03
clk: at91: rework PLL rate calculation
Boris BREZILLON
1
-70
/
+77
2014-09-03
clk: at91: fix PLL_MAX_COUNT macro definition
Boris BREZILLON
1
-1
/
+1
2013-12-02
clk: at91: add PMC master clock
Boris BREZILLON
1
-8
/
+2
2013-12-02
clk: at91: add PMC pll clocks
Boris BREZILLON
1
-0
/
+537