index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
at91
/
sama5d2.c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-12-19
clk: at91: clk-master: re-factor master clock
Claudiu Beznea
1
-15
/
+27
2020-07-24
clk: at91: clk-programmable: add mux_table option
Claudiu Beznea
1
-1
/
+2
2020-07-24
clk: at91: clk-peripheral: add support for changeable parent rate
Claudiu Beznea
1
-2
/
+3
2020-07-24
clk: at91: clk-generated: add mux_table option
Claudiu Beznea
1
-1
/
+1
2020-07-24
clk: at91: clk-generated: pass the id of changeable parent at registration
Claudiu Beznea
1
-16
/
+15
2020-05-27
clk: at91: allow setting all PMC clock parents via DT
Michał Mirosław
1
-1
/
+5
2020-05-27
clk: at91: allow setting PCKx parent via DT
Michał Mirosław
1
-1
/
+3
2020-05-27
clk: at91: optimize pmc data allocation
Michał Mirosław
1
-1
/
+1
2020-05-27
clk: at91: Add peripheral clock for PTC
Codrin Ciubotariu
1
-0
/
+1
2019-12-16
clk: at91: fix possible deadlock
Alexandre Belloni
1
-1
/
+1
2019-09-18
clk: at91: allow 24 Mhz clock as input for PLL
Eugen Hristev
1
-1
/
+1
2019-05-07
Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...
Stephen Boyd
1
-1
/
+11
2019-04-26
clk: at91: Mark struct clk_range as const
Stephen Boyd
1
-1
/
+1
2019-04-25
clk: at91: allow configuring generated PCR layout
Alexandre Belloni
1
-0
/
+1
2019-04-25
clk: at91: allow configuring peripheral PCR layout
Alexandre Belloni
1
-0
/
+9
2019-03-18
clk: at91: fix programmable clock for sama5d2
Matthias Wieloch
1
-1
/
+9
2019-03-08
Merge branch 'clk-at91' into clk-next
Stephen Boyd
1
-1
/
+2
2019-02-20
clk: at91: fix masterck name
Alexandre Belloni
1
-2
/
+2
2019-01-09
clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2
Michał Mirosław
1
-1
/
+2
2018-10-17
clk: at91: add sama5d2 PMC driver
Alexandre Belloni
1
-0
/
+336