index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
keystone
Age
Commit message (
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)
Author
Files
Lines
2019-07-17
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
2
-38
/
+212
2019-06-07
clk: keystone: sci-clk: extend clock IDs to 32 bits
Tero Kristo
1
-8
/
+28
2019-06-07
clk: keystone: sci-clk: probe clocks from DT instead of firmware
Tero Kristo
2
-0
/
+141
2019-06-07
clk: keystone: sci-clk: split out the fw clock parsing to own function
Tero Kristo
1
-27
/
+41
2019-06-07
clk: keystone: sci-clk: cut down the clock name length
Tero Kristo
1
-4
/
+3
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Thomas Gleixner
2
-10
/
+2
2019-05-21
treewide: Add SPDX license identifier - Makefile/Kconfig
Thomas Gleixner
2
-0
/
+2
2018-10-19
Merge branch 'clk-k3-tisci' into clk-next
Stephen Boyd
3
-1
/
+11
2018-10-08
clk: keystone: add missing MODULE_LICENSE
Arnd Bergmann
2
-0
/
+10
2018-10-02
clk: keystone: Enable TISCI clocks if K3_ARCH
Nishanth Menon
1
-1
/
+1
2018-08-30
clk: Convert to using %pOFn instead of device_node.name
Rob Herring
2
-2
/
+2
2018-03-08
clk: keystone: sci-clk: add support for dynamically probing clocks
Tero Kristo
1
-290
/
+90
2017-08-03
clk: keystone: sci-clk: Fix sci_clk_get
Tero Kristo
1
-24
/
+42
2017-06-23
clk: keystone: TI_SCI_PROTOCOL is needed for clk driver
Arnd Bergmann
1
-1
/
+2
2017-06-14
clk: keystone: Add sci-clk driver support
Tero Kristo
3
-1
/
+741
2016-12-09
clk: keystone: pll: Unmap region obtained by of_iomap
Arvind Yadav
1
-2
/
+7
2016-11-02
clk: keystone: improve function-level documentation
Julia Lawall
1
-2
/
+2
2015-10-20
clk: keystone: fix a trivial typo
Geliang Tang
1
-1
/
+1
2015-07-28
Merge branch 'cleanup-clk-h-includes' into clk-next
Stephen Boyd
2
-2
/
+0
2015-07-28
clk: keystone: make use of of_clk_parent_fill helper function
Dinh Nguyen
1
-2
/
+1
2015-07-20
clk: keystone: Remove clk.h include
Stephen Boyd
2
-2
/
+0
2015-06-19
clk: keystone: add support for post divider register for main pll
Murali Karicheri
1
-2
/
+18
2014-02-11
clk: keystone: gate: fix clk_init_data initialization
Ivan Khoronzhuk
1
-0
/
+1
2013-12-10
clk: keystone: gate: fix error handling on init
Grygorii Strashko
1
-4
/
+8
2013-12-10
clk: keystone: use clkod register bits for postdiv
Murali Karicheri
1
-4
/
+20
2013-10-08
clk: keystone: Build Keystone clock drivers
Santosh Shilimkar
1
-0
/
+1
2013-10-08
clk: keystone: Add gate control clock driver
Santosh Shilimkar
1
-0
/
+264
2013-10-08
clk: keystone: add Keystone PLL clock driver
Santosh Shilimkar
1
-0
/
+305