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path: root/drivers/clk/mediatek/clk-mt2701.c
AgeCommit message (Expand)AuthorFilesLines
2022-06-16clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen1-2/+2
2022-06-16clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen1-4/+7
2022-06-16clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen1-2/+17
2022-06-16clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen1-2/+2
2022-05-20clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai1-12/+14
2022-05-19clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen1-4/+4
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai1-2/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-02-25clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai1-2/+2
2018-08-31clk: mediatek: remove unused array audio_parentsColin Ian King1-5/+0
2018-05-16clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee1-2/+6
2018-03-19clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang1-7/+8
2017-11-02clk: mediatek: mark mtk_infrasys_init_early __initArnd Bergmann1-1/+1
2017-06-20clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang1-0/+8
2016-11-09reset: mediatek: Add MT2701 reset driverShunli Wang1-2/+10
2016-11-09clk: mediatek: Add MT2701 clock supportShunli Wang1-0/+1027