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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
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fedora-vic-7100_5.10.6
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openwrt-6.1.y
rt-ethercat-release
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starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
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visionfive
visionfive-5.13.y-devel
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visionfive-5.16.y
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visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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drivers
/
clk
/
meson
Age
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2019-05-07
Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...
Stephen Boyd
9
-516
/
+2171
2019-04-08
clk: meson: axg-audio: add g12a support
Maxime Jourdan
2
-8
/
+239
2019-04-08
clk: meson: axg-audio: don't register inputs in the onecell data
Jerome Brunet
2
-44
/
+6
2019-04-08
clk: meson: axg_audio: replace prefix axg by aud
Jerome Brunet
1
-482
/
+482
2019-04-01
clk: meson: meson8b: add the video decoder clock trees
Martin Blumenstingl
2
-1
/
+328
2019-04-01
clk: meson: meson8b: add the VPU clock trees
Martin Blumenstingl
2
-1
/
+175
2019-04-01
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
Martin Blumenstingl
2
-1
/
+66
2019-04-01
clk: meson: meson8b: use a separate clock table for Meson8m2
Martin Blumenstingl
1
-1
/
+192
2019-04-01
clk: meson-g12a: add video decoder clocks
Maxime Jourdan
2
-1
/
+170
2019-04-01
clk: meson-g12a: add PCIE PLL clocks
Neil Armstrong
2
-1
/
+122
2019-04-01
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
Neil Armstrong
2
-0
/
+27
2019-04-01
clk: meson: g12a: add cpu clocks
Neil Armstrong
2
-1
/
+371
2019-04-01
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
Neil Armstrong
1
-1
/
+0
2019-04-01
dt-bindings: clock: axg-audio: unexpose controller inputs
Jerome Brunet
1
-0
/
+20
2019-03-29
clk: meson: vid-pll-div: remove warning and return 0 on invalid config
Neil Armstrong
1
-2
/
+2
2019-03-25
clk: meson: pll: fix rounding and setting a rate that matches precisely
Martin Blumenstingl
1
-1
/
+1
2019-03-19
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
Neil Armstrong
1
-1
/
+0
2019-03-19
clk: meson-g12a: fix VPU clock parents
Neil Armstrong
1
-1
/
+1
2019-03-19
clk: meson: g12a: fix VPU clock muxes mask
Maxime Jourdan
1
-2
/
+2
2019-03-19
clk: meson-gxbb: round the vdec dividers to closest
Maxime Jourdan
1
-0
/
+2
2019-02-13
clk: meson: meson8b: fix the naming of the APB clocks
Martin Blumenstingl
2
-14
/
+14
2019-02-13
clk: meson: Add G12A AO Clock + Reset Controller
Neil Armstrong
4
-1
/
+491
2019-02-04
clk: meson: factorise meson64 peripheral clock controller drivers
Jerome Brunet
7
-176
/
+313
2019-02-04
clk: meson: g12a: add peripheral clock controller
Jian Hu
5
-2
/
+2594
2019-02-04
clk: meson: pll: update driver for the g12a
Jerome Brunet
2
-59
/
+154
2019-02-02
clk: meson: rework and clean drivers dependencies
Jerome Brunet
29
-281
/
+465
2019-02-02
clk: meson: axg-audio does not require syscon
Jerome Brunet
1
-1
/
+1
2019-01-18
clk: meson: ao-clkc: claim clock controller input clocks from DT
Jerome Brunet
4
-14
/
+82
2019-01-18
clk: meson: axg: claim clock controller input clock from DT
Jerome Brunet
1
-8
/
+19
2019-01-18
clk: meson: gxbb: claim clock controller input clock from DT
Jerome Brunet
1
-13
/
+24
2019-01-07
clk: meson: meson8b: add the GPU clock tree
Martin Blumenstingl
2
-1
/
+154
2019-01-07
clk: meson: meson8b: use a separate clock table for Meson8
Martin Blumenstingl
1
-6
/
+197
2019-01-07
clk: meson: axg-ao: add 32k generation subtree
Jerome Brunet
2
-25
/
+163
2019-01-07
clk: meson: gxbb-ao: replace cec-32k with the dual divider
Jerome Brunet
4
-262
/
+204
2019-01-07
clk: meson: add dual divider clock driver
Jerome Brunet
3
-1
/
+150
2019-01-07
clk: meson: clean-up clock registration
Jerome Brunet
1
-5
/
+10
2018-12-15
Merge branch 'clk-fixes' into clk-next
Stephen Boyd
2
-0
/
+25
2018-12-13
Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...
Stephen Boyd
7
-71
/
+870
2018-12-11
clk: meson: axg-audio: use the clk input helper function
Jerome Brunet
1
-59
/
+24
2018-12-05
clk: meson: add clk-input helper function
Jerome Brunet
3
-0
/
+50
2018-12-04
clk: meson: Mark some things static
Stephen Boyd
2
-6
/
+6
2018-12-03
clk: meson: meson8b: add the read-only video clock trees
Martin Blumenstingl
2
-10
/
+782
2018-12-03
clk: meson: meson8b: add the fractional divider for vid_pll_dco
Martin Blumenstingl
2
-0
/
+6
2018-12-03
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
Martin Blumenstingl
1
-1
/
+1
2018-11-27
clk: meson: Fix GXL HDMI PLL fractional bits width
Neil Armstrong
1
-1
/
+7
2018-11-23
clk: meson: meson8b: add the CPU clock post divider clocks
Martin Blumenstingl
2
-1
/
+256
2018-11-23
clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
Martin Blumenstingl
2
-12
/
+12
2018-11-23
clk: meson: clk-regmap: add read-only gate ops
Martin Blumenstingl
2
-0
/
+6
2018-11-23
clk: meson: meson8b: allow changing the CPU clock tree
Martin Blumenstingl
1
-6
/
+6
2018-11-23
clk: meson: meson8b: run from the XTAL when changing the CPU frequency
Martin Blumenstingl
1
-0
/
+63
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