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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
/
r8a779f0-cpg-mssr.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-02-13
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
Geert Uytterhoeven
1
-1
/
+1
2022-11-16
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
Geert Uytterhoeven
1
-2
/
+2
2022-11-08
clk: renesas: r8a779f0: Fix SCIF parent clocks
Wolfram Sang
1
-4
/
+4
2022-11-08
clk: renesas: r8a779f0: Fix HSCIF parent clocks
Wolfram Sang
1
-4
/
+4
2022-10-26
clk: renesas: r8a779f0: Add SASYNCPER internal clock
Geert Uytterhoeven
1
-3
/
+5
2022-10-26
clk: renesas: r8a779f0: Fix SD0H clock name
Geert Uytterhoeven
1
-1
/
+1
2022-10-17
clk: renesas: r8a779f0: Add Ethernet Switch clocks
Yoshihiro Shimoda
1
-0
/
+2
2022-08-29
clk: renesas: r8a779f0: Add MSIOF clocks
Wolfram Sang
1
-0
/
+4
2022-08-22
clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
Wolfram Sang
1
-0
/
+10
2022-08-15
clk: renesas: r8a779f0: Add CMT clocks
Wolfram Sang
1
-0
/
+4
2022-08-15
clk: renesas: r8a779f0: Add SDH0 clock
Wolfram Sang
1
-1
/
+2
2022-06-17
clk: renesas: r8a779f0: Add HSCIF clocks
Wolfram Sang
1
-0
/
+4
2022-06-17
clk: renesas: r8a779f0: Add PCIe clocks
Yoshihiro Shimoda
1
-0
/
+2
2022-06-17
clk: renesas: r8a779f0: Add Z0 and Z1 clock support
Geert Uytterhoeven
1
-0
/
+2
2022-06-13
clk: renesas: r8a779f0: Add SDHI0 clock
Wolfram Sang
1
-0
/
+1
2022-06-13
clk: renesas: r8a779f0: Add thermal clock
Wolfram Sang
1
-0
/
+1
2022-04-29
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
Yoshihiro Shimoda
1
-10
/
+10
2022-04-25
clk: renesas: r8a779f0: Add UFS clock
Yoshihiro Shimoda
1
-0
/
+1
2022-04-13
clk: renesas: Move RPC core clocks
Geert Uytterhoeven
1
-3
/
+6
2022-02-22
clk: renesas: r8a779f0: Add PFC clock
Geert Uytterhoeven
1
-0
/
+1
2022-02-22
clk: renesas: r8a779f0: Add I2C clocks
Geert Uytterhoeven
1
-0
/
+6
2022-02-22
clk: renesas: r8a779f0: Add WDT clock
Geert Uytterhoeven
1
-0
/
+9
2022-02-22
clk: renesas: r8a779f0: Fix RSW2 clock divider
Geert Uytterhoeven
1
-1
/
+1
2022-01-24
clk: renesas: r8a779f0: Add SYS-DMAC clocks
Yoshihiro Shimoda
1
-0
/
+2
2021-12-08
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Yoshihiro Shimoda
1
-0
/
+183