index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
/
r9a06g032-clocks.c
Age
Commit message (
Expand
)
Author
Files
Lines
2021-05-11
clk: renesas: r9a06g032: Switch to .determine_rate()
Geert Uytterhoeven
1
-12
/
+13
2021-03-30
clk: renesas: Zero init clk_init_data
Geert Uytterhoeven
1
-4
/
+4
2021-03-24
clk: renesas: Couple of spelling fixes
Bhaskar Chowdhury
1
-2
/
+2
2020-12-08
clk: renesas: r9a06g032: Drop __packed for portability
Geert Uytterhoeven
1
-1
/
+1
2020-04-14
clk: renesas: r9a06g032: Fix some typo in comments
Christophe JAILLET
1
-3
/
+3
2019-08-23
clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
Geert Uytterhoeven
1
-1
/
+2
2019-06-04
clk: renesas: r9a06g032: Add clock domain support
Gareth Williams
1
-69
/
+158
2019-05-15
clk: Remove io.h from clk-provider.h
Stephen Boyd
1
-0
/
+1
2019-04-02
clk: renesas: r9a06g032: Add missing PCI USB clock
Gareth Williams
1
-0
/
+1
2018-12-11
clk: renesas: Remove usage of CLK_IS_BASIC
Stephen Boyd
1
-4
/
+4
2018-09-11
clk: renesas: r9a06g032: Fix UART34567 clock rate
Phil Edworthy
1
-1
/
+2
2018-06-25
clk: renesas: Renesas R9A06G032 clock driver
Michel Pollet
1
-0
/
+893