index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
Age
Commit message (
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)
Author
Files
Lines
2019-05-07
Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...
Stephen Boyd
3
-6
/
+6
2019-05-01
clk: renesas: Use the correct style for SPDX License Identifier
Nishad Kamdar
3
-6
/
+6
2019-04-11
clk: renesas: rcar-gen3: Remove unused variable
Stephen Boyd
1
-1
/
+0
2019-04-04
clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
Takeshi Kihara
1
-16
/
+14
2019-04-02
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
Sergei Shtylyov
1
-1
/
+1
2019-04-02
clk: renesas: rcar-gen3: Rename DRIF clocks
Takeshi Kihara
4
-34
/
+35
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
Takeshi Kihara
7
-11
/
+11
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
Takeshi Kihara
4
-8
/
+8
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
Kazuya Mizuguchi
6
-7
/
+7
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
Kazuya Mizuguchi
6
-12
/
+12
2019-04-02
clk: renesas: r8a774c0: Add Z2 clock
Simon Horman
1
-0
/
+1
2019-04-02
clk: renesas: r8a77990: Add Z2 clock
Takeshi Kihara
1
-0
/
+1
2019-04-02
clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
Simon Horman
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
Simon Horman
5
-5
/
+3
2019-04-02
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
Simon Horman
6
-20
/
+13
2019-04-02
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
Takeshi Kihara
6
-16
/
+28
2019-04-02
clk: renesas: r9a06g032: Add missing PCI USB clock
Gareth Williams
1
-0
/
+1
2019-04-02
clk: renesas: r7s9210: Always use readl()
Geert Uytterhoeven
1
-1
/
+2
2019-03-18
clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
Geert Uytterhoeven
1
-6
/
+6
2019-02-25
clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK
Fabrizio Castro
1
-1
/
+1
2019-02-22
clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
Fabrizio Castro
1
-1
/
+1
2019-02-05
clk: renesas: r8a774c0: Add TMU clock
Biju Das
1
-0
/
+5
2019-02-05
clk: renesas: r8a77980: Add RPC clocks
Sergei Shtylyov
1
-0
/
+8
2019-02-05
clk: renesas: rcar-gen3: Add RPC clocks
Sergei Shtylyov
2
-0
/
+105
2019-01-25
clk: renesas: rcar-gen3: Add spinlock
Sergei Shtylyov
1
-0
/
+8
2019-01-25
clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
Sergei Shtylyov
1
-18
/
+20
2019-01-24
clk: renesas: r8a774c0: Correct parent clock of DU
Geert Uytterhoeven
1
-2
/
+2
2019-01-21
clk: renesas: r8a774a1: Add missing CANFD clock
Fabrizio Castro
1
-0
/
+2
2019-01-21
clk: renesas: r8a774c0: Add missing CANFD clock
Fabrizio Castro
1
-0
/
+4
2018-12-15
Merge branch 'clk-of' into clk-next
Stephen Boyd
1
-1
/
+1
2018-12-15
clk: Use of_node_name_eq for node name comparisons
Rob Herring
1
-1
/
+1
2018-12-15
Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...
Stephen Boyd
9
-34
/
+58
2018-12-11
clk: renesas: Remove usage of CLK_IS_BASIC
Stephen Boyd
5
-8
/
+8
2018-12-07
Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/...
Stephen Boyd
8
-33
/
+46
2018-12-07
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
Niklas Söderlund
1
-7
/
+26
2018-12-07
clk: renesas: rcar-gen3: Add documentation for SD clocks
Niklas Söderlund
1
-5
/
+5
2018-12-07
clk: renesas: rcar-gen3: Set state when registering SD clocks
Niklas Söderlund
1
-12
/
+4
2018-12-04
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
Geert Uytterhoeven
1
-2
/
+2
2018-12-04
clk: renesas: r8a77995: Add missing CPEX clock
Geert Uytterhoeven
1
-1
/
+2
2018-12-04
clk: renesas: r8a77995: Remove non-existent SSP clocks
Geert Uytterhoeven
1
-1
/
+0
2018-12-04
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
Geert Uytterhoeven
1
-3
/
+0
2018-12-04
clk: renesas: r8a77995: Correct parent clock of DU
Geert Uytterhoeven
1
-2
/
+2
2018-12-04
clk: renesas: r8a77990: Correct parent clock of DU
Takeshi Kihara
1
-2
/
+2
2018-12-04
clk: renesas: r8a77970: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a77965: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a7796: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a7795: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a774a1: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-11-30
clk: renesas: Mark rza2_cpg_clk_register static
Stephen Boyd
1
-1
/
+1
2018-11-13
clk: renesas: r7s9210: Add USB clocks
Chris Brandt
1
-0
/
+2
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