starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-05-29	Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	1	-1/+39
2022-05-19	clk: renesas: r9a06g032: Probe possible children	Miquel Raynal	1	-0/+5
2022-05-19	clk: renesas: r9a06g032: Export function to set dmamux	Miquel Raynal	1	-1/+34
2022-05-06	clk: renesas: r9a09g011: Add eth clock and reset entries	Phil Edworthy	1	-5/+9
2022-05-06	clk: renesas: Add RZ/V2M support using the rzg2l driver	Phil Edworthy	5	-0/+181
2022-05-05	clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg	Phil Edworthy	2	-3/+17
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	4	-1/+16
2022-05-05	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	3	-31/+19
2022-05-05	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	3	-6/+12
2022-05-05	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	3	-22/+19
2022-05-05	clk: renesas: r9a07g044: Fix OSTM1 module clock name	Geert Uytterhoeven	1	-1/+1
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for ADC	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add TSU clock and reset entry	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add RSPI clock and reset entries	Biju Das	1	-0/+9
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...	Biju Das	1	-0/+18
2022-05-05	clk: renesas: r9a07g044: Add DSI clock and reset entries	Biju Das	1	-1/+16
2022-05-05	clk: renesas: r9a07g044: Add LCDC clock and reset entries	Biju Das	1	-1/+8
2022-05-05	clk: renesas: r9a07g044: Add M4 Clock support	Biju Das	1	-1/+18
2022-05-05	clk: renesas: r9a07g044: Add M3 Clock support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add M1 clock support	Biju Das	1	-1/+10
2022-05-05	clk: renesas: rzg2l: Add DSI divider clk support	Biju Das	2	-0/+136
2022-05-05	clk: renesas: rzg2l: Add PLL5_4 clk mux support	Biju Das	2	-0/+103
2022-05-05	clk: renesas: rzg2l: Add FOUTPOSTDIV clk support	Biju Das	2	-0/+235
2022-04-29	clk: renesas: cpg-mssr: Add support for R-Car V4H	Yoshihiro Shimoda	5	-0/+231
2022-04-29	clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4	Yoshihiro Shimoda	4	-16/+24
2022-04-28	clk: renesas: r9a07g043: Add WDT clock and reset entries	Biju Das	1	-0/+10
2022-04-28	clk: renesas: r9a07g043: Add OSTM clock and reset entries	Biju Das	1	-0/+9
2022-04-28	clk: renesas: r9a07g043: Add clock and reset entries for CANFD	Biju Das	1	-0/+5
2022-04-28	clk: renesas: r9a07g043: Add USB clocks/resets	Biju Das	1	-0/+12
2022-04-28	clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries	Biju Das	1	-0/+20
2022-04-28	clk: renesas: r9a07g043: Add I2C clocks/resets	Biju Das	1	-0/+12
2022-04-28	clk: renesas: r9a06g032: Fix the RTC hclock description	Miquel Raynal	1	-1/+1
2022-04-25	clk: renesas: r8a779f0: Add UFS clock	Yoshihiro Shimoda	1	-0/+1
2022-04-13	clk: renesas: r9a07g043: Add SDHI clock and reset entries	Biju Das	1	-0/+35
2022-04-13	clk: renesas: r9a07g043: Add GbEthernet clock/reset	Biju Das	1	-0/+10
2022-04-13	clk: renesas: r9a07g043: Add ethernet clock sources	Biju Das	1	-0/+13
2022-04-13	clk: renesas: r9a07g043: Add GPIO clock and reset entries	Biju Das	1	-0/+5
2022-04-13	clk: renesas: Add support for RZ/G2UL SoC	Biju Das	5	-1/+171
2022-04-13	clk: renesas: Move RPC core clocks	Geert Uytterhoeven	12	-57/+51
2022-04-13	clk: renesas: rzg2l: Simplify multiplication/shift logic	Geert Uytterhoeven	1	-1/+1
2022-04-11	clk: renesas: r8a77995: Add RPC clocks	Geert Uytterhoeven	2	-1/+13
2022-04-11	clk: renesas: r8a77990: Add RPC clocks	Geert Uytterhoeven	1	-0/+9
2022-04-04	clk: renesas: rzg2l: Remove unused notifiers	Phil Edworthy	1	-2/+0
2022-02-22	clk: renesas: r8a779f0: Add PFC clock	Geert Uytterhoeven	1	-0/+1
2022-02-22	clk: renesas: r8a779f0: Add I2C clocks	Geert Uytterhoeven	1	-0/+6
2022-02-22	clk: renesas: r8a779f0: Add WDT clock	Geert Uytterhoeven	1	-0/+9
2022-02-22	clk: renesas: r8a779f0: Fix RSW2 clock divider	Geert Uytterhoeven	1	-1/+1
2022-02-10	clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC	Biju Das	5	-191/+250
2022-01-24	clk: renesas: r8a779a0: Add CANFD module clock	Ulrich Hecht	1	-0/+1