| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-05-03 | clk: rockchip: Mark hclk_vo as critical on rk3568 | Sascha Hauer | 1 | -0/+1 |
| 2022-02-24 | clk/rockchip: Use of_device_get_match_data() | Minghao Chi (CGEL ZTE) | 1 | -4/+2 |
| 2022-02-08 | clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 | Sascha Hauer | 1 | -1/+1 |
| 2022-02-08 | clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 | Sascha Hauer | 1 | -3/+3 |
| 2022-02-08 | clk: rockchip: Add more PLL rates for rk3568 | Sascha Hauer | 1 | -0/+6 |
| 2021-11-03 | clk: rockchip: drop module parts from rk3399 and rk3568 drivers | Heiko Stuebner | 1 | -4/+0 |
| 2021-11-03 | Revert "clk: rockchip: use module_platform_driver_probe" | Heiko Stuebner | 1 | -1/+1 |
| 2021-09-21 | clk: rockchip: use module_platform_driver_probe | Miles Chen | 1 | -1/+1 |
| 2021-05-24 | clk: rockchip: fix rk3568 cpll clk gate bits | Peter Geis | 1 | -5/+5 |
| 2021-03-21 | clk: rockchip: add clock controller for rk3568 | Elaine Zhang | 1 | -0/+1725 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |