index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
socfpga
/
clk-agilex.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-08-23
clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
Yangtao Li
1
-3
/
+1
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-2
/
+1
2022-01-06
clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_r...
Cai Huoqing
1
-3
/
+1
2021-09-25
clk: socfpga: agilex: fix duplicate s2f_user0_clk
Dinh Nguyen
1
-9
/
+0
2021-07-27
clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
Dinh Nguyen
1
-1
/
+1
2021-07-27
clk: socfpga: agilex: fix up s2f_user0_clk representation
Dinh Nguyen
1
-0
/
+9
2021-07-27
clk: socfpga: agilex: fix the parents of the psi_ref_clk
Dinh Nguyen
1
-4
/
+4
2021-06-28
clk: agilex/stratix10: add support for the 2nd bypass
Dinh Nguyen
1
-1
/
+3
2021-06-28
clk: agilex/stratix10: fix bypass representation
Dinh Nguyen
1
-11
/
+46
2021-06-28
clk: agilex/stratix10: remove noc_clk
Dinh Nguyen
1
-17
/
+15
2021-03-31
clk: socfpga: Fix code formatting
Stephen Boyd
1
-1
/
+2
2021-03-31
clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
Dinh Nguyen
1
-54
/
+60
2021-02-13
clk: socfpga: agilex: add clock driver for eASIC N5X platform
Dinh Nguyen
1
-2
/
+86
2020-09-22
clk: socfpga: agilex: Remove unused variable 'cntr_mux'
YueHaibing
1
-13
/
+0
2020-06-20
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
Dinh Nguyen
1
-1
/
+1
2020-06-20
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
Dinh Nguyen
1
-1
/
+5
2020-05-27
clk: socfpga: agilex: add clock driver for the Agilex platform
Dinh Nguyen
1
-0
/
+454