index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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commit
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log msg
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path:
root
/
drivers
/
clk
/
socfpga
/
clk-s10.c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-09-22
clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk
Dinh Nguyen
1
-1
/
+1
2020-05-27
clk: socfpga: stratix10: use new parent data scheme
Dinh Nguyen
1
-29
/
+131
2020-02-13
clk: socfpga: stratix10: simplify parameter passing
Dinh Nguyen
1
-25
/
+4
2019-06-26
clk: socfpga: stratix10: fix divider entry for the emac clocks
Dinh Nguyen
1
-2
/
+2
2019-06-26
clk: socfpga: stratix10: add additional clocks needed for the NAND IP
Dinh Nguyen
1
-1
/
+5
2019-01-15
clk: socfpga: stratix10: fix naming convention for the fixed-clocks
Dinh Nguyen
1
-10
/
+10
2018-07-06
clk: socfpga: stratix10: fix the sdmmc_free_clk mux
Dinh Nguyen
1
-1
/
+1
2018-07-06
clk: socfpga: stratix10: fix the parents of mpu_free_clk
Dinh Nguyen
1
-1
/
+6
2018-05-16
clk: socfpga: stratix10: suppress unbinding platform's clock driver
Dinh Nguyen
1
-0
/
+1
2018-05-16
clk: socfpga: stratix10: use platform driver APIs
Dinh Nguyen
1
-22
/
+17
2018-04-06
clk: socfpga: stratix10: add clock driver for Stratix10 platform
Dinh Nguyen
1
-0
/
+345