index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
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path:
root
/
drivers
/
clk
/
socfpga
Age
Commit message (
Expand
)
Author
Files
Lines
2015-08-25
clk: socfpga: Add a second parent option for the dbg_base_clk
Dinh Nguyen
2
-4
/
+15
2015-07-28
clk: socfpga: switch to GENMASK()
Andy Shevchenko
5
-5
/
+4
2015-07-20
clk: socfpga: Remove clk.h and clkdev.h includes
Stephen Boyd
7
-7
/
+6
2015-06-10
clk: socfpga: remove a stray tab
Dan Carpenter
1
-1
/
+1
2015-06-06
clk: socfpga: make use of of_clk_parent_fill helper function
Dinh Nguyen
2
-11
/
+2
2015-05-22
clk: socfpga: add a clock driver for the Arria 10 platform
Dinh Nguyen
6
-1
/
+469
2015-05-22
clk: socfpga: update clk.h so for Arria10 platform to use
Dinh Nguyen
2
-5
/
+5
2015-05-15
clk: socfpga: Silence sparse warning
Stephen Boyd
1
-1
/
+1
2015-05-15
clk: socfpga: Silence sparse warning
Stephen Boyd
1
-1
/
+1
2014-05-13
Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-...
Mike Turquette
3
-4
/
+23
2014-05-12
clk: socfpga: add divider registers to the main pll outputs
Dinh Nguyen
3
-4
/
+23
2014-04-30
clk: socfpga: fix clock driver for 3.15
Dinh Nguyen
2
-20
/
+10
2014-03-19
clk: socfpga: Fix section mismatch warning
Dinh Nguyen
1
-1
/
+1
2014-02-27
clk: socfpga: Support multiple parents for the pll clocks
Dinh Nguyen
1
-4
/
+22
2014-02-27
clk: socfpga: Fix integer overflow in clock calculation
Dinh Nguyen
1
-3
/
+5
2014-02-19
clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"
Dinh Nguyen
1
-0
/
+68
2014-02-19
clk: socfpga: split clk code
Steffen Trumtrar
6
-306
/
+462
2014-02-19
clk: socfpga: fix define typo
Steffen Trumtrar
1
-3
/
+3
2014-02-19
clk: socfpga: remove unused field
Steffen Trumtrar
1
-1
/
+0
2014-02-19
clk: socfpga: Remove socfpga_init_clocks
Dinh Nguyen
1
-10
/
+0
2014-02-19
clk: socfpga: Look for the GPIO_DB_CLK by its offset
Dinh Nguyen
1
-2
/
+3
2014-02-19
clk: socfpga: Map the clk manager base address in the clock driver
Dinh Nguyen
1
-4
/
+16
2013-12-20
clk: socfpga: Use NULL instead of 0
Sachin Kamat
1
-1
/
+1
2013-11-28
clk: socfpga: Remove check for "reg" property in socfpga_clk_init
Dinh Nguyen
1
-3
/
+1
2013-10-08
clk: socfpga: Fix incorrect sdmmc clock name
Dinh Nguyen
1
-1
/
+1
2013-06-12
ARM: socfpga: Add support to gate peripheral clocks
Dinh Nguyen
1
-9
/
+185
2013-04-15
ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries
Dinh Nguyen
1
-21
/
+142
2012-07-19
ARM: socfpga: initial support for Altera's SOCFPGA platform
Dinh Nguyen
2
-0
/
+52