index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
st
Age
Commit message (
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)
Author
Files
Lines
2015-10-09
drivers: clk: st: Correct the pll-type for A9 for stih418
Gabriel Fernandez
1
-0
/
+194
2015-10-09
drivers: clk: st: PLL rate change implementation for DVFS
Gabriel Fernandez
3
-10
/
+216
2015-10-09
drivers: clk: st: Support for enable/disable in Clockgen PLLs
Gabriel Fernandez
1
-1
/
+59
2015-10-02
clk: st: fix handling result of of_property_count_strings
Andrzej Hajda
1
-3
/
+4
2015-09-17
drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Gabriel Fernandez
2
-10
/
+10
2015-08-25
clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
Stephen Boyd
4
-16
/
+16
2015-08-25
clk: Convert __clk_get_flags() to clk_hw_get_flags()
Stephen Boyd
1
-1
/
+1
2015-07-28
Merge branch 'cleanup-clk-h-includes' into clk-next
Stephen Boyd
4
-0
/
+4
2015-07-28
clk: st: make use of of_clk_parent_fill helper function
Dinh Nguyen
2
-9
/
+4
2015-07-20
clk: st: Include clk.h
Stephen Boyd
4
-0
/
+4
2015-07-14
clk: st: Fix error paths and allocation style
Stephen Boyd
1
-38
/
+45
2015-07-08
drivers: clk: st: Incorrect register offset used for lock_status
Pankaj Dev
1
-1
/
+1
2015-07-06
drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
Gabriel Fernandez
1
-1
/
+1
2015-07-06
drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
Pankaj Dev
4
-6
/
+8
2015-07-06
drivers: clk: st: Fix flexgen lock init
Giuseppe Cavallaro
1
-0
/
+2
2015-07-06
drivers: clk: st: Fix FSYN channel values
Gabriel Fernandez
1
-2
/
+2
2015-07-06
drivers: clk: st: Remove unused code
Gabriel Fernandez
1
-4
/
+0
2015-06-04
clk: st: Use of_clk_get_parent_count() instead of open coding
Geert Uytterhoeven
2
-2
/
+2
2015-05-15
clk: st: Silence sparse warnings
Stephen Boyd
4
-17
/
+17
2015-04-01
clk: constify of_device_id array
Fabian Frederick
3
-7
/
+7
2015-02-18
clk: Replace explicit clk assignment with __clk_hw_set_clk
Javier Martinez Canillas
2
-17
/
+17
2015-01-20
clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate
Peter Griffin
1
-4
/
+15
2014-07-29
clk: st: Use round to closest divider flag
Gabriel FERNANDEZ
1
-1
/
+2
2014-07-29
clk: st: Update frequency tables for fs660c32 and fs432c65
Gabriel FERNANDEZ
1
-8
/
+59
2014-07-29
clk: st: STiH407: Support for clockgenA9
Gabriel FERNANDEZ
1
-0
/
+16
2014-07-29
clk: st: STiH407: Support for clockgenD0/D2/D3
Gabriel FERNANDEZ
1
-0
/
+46
2014-07-29
clk: st: STiH407: Support for clockgenC0
Gabriel FERNANDEZ
2
-0
/
+83
2014-07-29
clk: st: Add quadfs reset handling
Gabriel FERNANDEZ
1
-0
/
+5
2014-07-29
clk: st: Add polarity bit indication
Gabriel FERNANDEZ
1
-5
/
+7
2014-07-29
clk: st: STiH407: Support for clockgenA0
Gabriel FERNANDEZ
1
-0
/
+16
2014-07-29
clk: st: STiH407: Support for A9 MUX Clocks
Gabriel FERNANDEZ
1
-0
/
+9
2014-07-29
clk: st: STiH407: Support for Flexgen Clocks
Gabriel FERNANDEZ
2
-1
/
+332
2014-07-29
clk: st: Remove uncessary (void *) cast
Gabriel FERNANDEZ
1
-4
/
+4
2014-07-29
clk: st: use static const for clkgen_pll_data tables
Gabriel FERNANDEZ
1
-16
/
+14
2014-07-29
clk: st: use static const for stm_fs tables
Gabriel FERNANDEZ
1
-17
/
+17
2014-05-28
clk: st: Terminate of match table
Stephen Boyd
1
-0
/
+1
2014-05-24
clk: st: Fix memory leak
Valentin Ilie
1
-1
/
+3
2014-03-26
clk: st: Support for A9 MUX clocks
Gabriel FERNANDEZ
1
-0
/
+19
2014-03-26
clk: st: Support for ClockGenA9/DDR/GPU
Gabriel FERNANDEZ
1
-0
/
+139
2014-03-26
clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
Gabriel FERNANDEZ
2
-1
/
+1040
2014-03-26
clk: st: Support for VCC-mux and MUX clocks
Gabriel FERNANDEZ
1
-0
/
+272
2014-03-26
clk: st: Support for PLLs inside ClockGenA(s)
Gabriel FERNANDEZ
3
-1
/
+608
2014-03-26
clk: st: Support for DIVMUX and PreDiv Clocks
Gabriel FERNANDEZ
2
-0
/
+530