Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2023-01-09 | clk: sunxi-ng: d1: Add CAN bus gates and resets | Fabien Poussin | 1 | -0/+11 |
2023-01-09 | clk: sunxi-ng: d1: Mark cpux clock as critical | András Szemző | 1 | -1/+1 |
2022-08-26 | clk: sunxi-ng: d1: Limit PLL rates to stable ranges | Samuel Holland | 1 | -0/+8 |
2021-11-23 | clk: sunxi-ng: Add support for the D1 SoC clocks | Samuel Holland | 1 | -0/+1390 |