index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
sunxi-ng
/
ccu-sun6i-a31.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-04-16
clk: sunxi-ng: fix module autoloading
Krzysztof Kozlowski
1
-0
/
+1
2021-11-23
clk: sunxi-ng: Convert early providers to platform drivers
Samuel Holland
1
-10
/
+30
2021-09-13
clk: sunxi-ng: Unregister clocks/resets when unbinding
Samuel Holland
1
-1
/
+1
2019-07-17
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-14
/
+25
2019-06-18
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-14
/
+25
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282
Thomas Gleixner
1
-9
/
+1
2019-05-15
clk: Remove io.h from clk-provider.h
Stephen Boyd
1
-0
/
+1
2019-01-28
clk: sunxi: A31: Fix wrong AHB gate number
Andre Przywara
1
-2
/
+2
2018-02-19
clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops
Chen-Yu Tsai
1
-3
/
+3
2017-10-13
clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL
Chen-Yu Tsai
1
-13
/
+25
2017-09-29
clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision
Chen-Yu Tsai
1
-1
/
+1
2017-07-22
clk: Convert to using %pOF instead of full_name
Rob Herring
1
-2
/
+1
2017-06-07
clk: sunxi-ng: Support multiple variable pre-dividers
Chen-Yu Tsai
1
-5
/
+5
2017-05-14
clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
Chen-Yu Tsai
1
-1
/
+1
2017-03-06
clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
Chen-Yu Tsai
1
-1
/
+1
2017-01-03
clk: sunxi-ng: A31: Fix spdif clock register
Marcus Cooper
1
-2
/
+2
2016-11-21
clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
Chen-Yu Tsai
1
-1
/
+1
2016-10-19
clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
Chen-Yu Tsai
1
-0
/
+12
2016-09-17
clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk
Chen-Yu Tsai
1
-1
/
+1
2016-09-17
clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs
Chen-Yu Tsai
1
-10
/
+10
2016-09-17
clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks
Chen-Yu Tsai
1
-9
/
+13
2016-08-25
clk: sunxi-ng: Add A31/A31s clocks
Chen-Yu Tsai
1
-0
/
+1235