index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
Age
Commit message (
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)
Author
Files
Lines
2015-10-20
Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Michael Turquette
7
-113
/
+163
2015-10-20
clk: tegra: Modify tegra_audio_clk_init to accept more plls
Rhyland Klein
5
-11
/
+56
2015-10-20
clk: tegra: Update struct tegra_clk_pll_params kerneldoc
Thierry Reding
1
-3
/
+15
2015-10-20
clk: tegra: Fix comments for structure definitions
Rhyland Klein
1
-37
/
+37
2015-10-20
clk: tegra: dfll: Monitor code is DEBUG_FS only
Thierry Reding
1
-50
/
+49
2015-10-12
clk: tegra: delete unneeded of_node_put
Julia Lawall
1
-3
/
+1
2015-09-17
clk: tegra: dfll: Properly protect OPP list
Thierry Reding
1
-1
/
+7
2015-09-15
clk: tegra: Unlock top rates for Tegra124 DFLL clock
Mikko Perttunen
2
-14
/
+8
2015-08-26
clk: tegra: Fix some static checker problems
Stephen Boyd
2
-7
/
+9
2015-08-26
Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Stephen Boyd
10
-9
/
+2304
2015-08-25
clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
Stephen Boyd
1
-4
/
+4
2015-08-25
clk: tegra: Convert to clk_hw based provider APIs
Stephen Boyd
2
-10
/
+10
2015-07-28
Merge branch 'cleanup-clk-h-includes' into clk-next
Stephen Boyd
16
-16
/
+2
2015-07-28
clk: change clk_ops' ->determine_rate() prototype
Boris Brezillon
1
-13
/
+15
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
16
-16
/
+2
2015-07-16
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
Tuomas Tynkkynen
1
-1
/
+3
2015-07-16
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
Tuomas Tynkkynen
1
-0
/
+14
2015-07-16
clk: tegra: Add Tegra124 DFLL clocksource platform driver
Tuomas Tynkkynen
4
-4
/
+172
2015-07-16
clk: tegra: Add DFLL DVCO reset control for Tegra124
Paul Walmsley
1
-0
/
+68
2015-07-16
clk: tegra: Introduce ability for SoC-specific reset control callbacks
Mikko Perttunen
2
-8
/
+34
2015-07-16
clk: tegra: Add functions for parsing CVB tables
Tuomas Tynkkynen
2
-0
/
+207
2015-07-16
clk: tegra: Add closed loop support for the DFLL
Tuomas Tynkkynen
1
-3
/
+663
2015-07-16
clk: tegra: Add library for the DFLL clock source (open-loop mode)
Tuomas Tynkkynen
3
-0
/
+1150
2015-05-13
clk: tegra: Fix hda2codec_2x clock name for Tegra30
Marcel Ziswiler
1
-1
/
+1
2015-05-13
clk: tegra: EMC clock driver depends on EMC driver
Thierry Reding
3
-1
/
+14
2015-05-13
clk: tegra: Have EMC clock implement determine_rate()
Tomeu Vizoso
1
-12
/
+23
2015-05-13
clk: tegra: Set the EMC clock as the parent of the MC clock
Tomeu Vizoso
1
-12
/
+1
2015-05-13
clk: tegra: Add EMC clock driver
Mikko Perttunen
4
-2
/
+535
2015-05-13
clk: tegra: Remove old Tegra124 EMC clock
Mikko Perttunen
1
-1
/
+0
2015-04-10
clk: tegra: Use the proper parent for plld_dsi
Thierry Reding
1
-6
/
+8
2015-04-10
clk: tegra: Use generic tegra_osc_clk_init() on Tegra114
Thierry Reding
1
-31
/
+3
2015-04-10
clk: tegra: Model oscillator as clock
Thierry Reding
4
-17
/
+21
2015-04-10
clk: tegra: Add peripheral registers for bank Y
Thierry Reding
1
-0
/
+14
2015-04-10
clk: tegra: Register the proper number of resets
Thierry Reding
1
-1
/
+1
2015-04-10
clk: tegra: Remove needless initializations
Thierry Reding
1
-3
/
+3
2015-04-10
clk: tegra: Use consistent indentation
Thierry Reding
1
-10
/
+10
2015-04-10
clk: tegra: Various whitespace cleanups
Thierry Reding
2
-1
/
+2
2015-04-10
clk: tegra: Enable HDA to HDMI clocks on Tegra124
Dylan Reid
1
-0
/
+5
2015-04-10
clk: tegra: Fix a bunch of sparse warnings
Thierry Reding
1
-1
/
+1
2015-04-10
clk: tegra: Fix typo tabel -> table
Thierry Reding
1
-1
/
+1
2015-02-18
clk: Replace explicit clk assignment with __clk_hw_set_clk
Javier Martinez Canillas
1
-7
/
+7
2015-02-02
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
Mark Zhang
4
-26
/
+24
2015-02-02
clk: tegra: Add support for the Tegra132 CAR IP block
Paul Walmsley
3
-12
/
+129
2015-02-02
clk: tegra: make tegra_clocks_apply_init_table() arch_initcall
Peter De Schrijver
1
-2
/
+5
2015-02-02
clk: tegra: Fix order of arguments in WARN
Tomeu Vizoso
1
-4
/
+4
2015-02-02
clk: tegra124: Add init data for dsi lp clocks
Sean Paul
1
-0
/
+2
2015-02-02
clk: tegra: SDMMC controllers are on APB
Andrew Bresticker
1
-8
/
+8
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
6
-4
/
+40
2014-09-18
clk: tegra: Make clock initialization more robust
Tomeu Vizoso
1
-2
/
+7
2014-09-18
clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks
Mikko Perttunen
1
-0
/
+8
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