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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
cxl
/
core
/
pci.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-02-17
cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window
Robert Richter
1
-3
/
+3
2024-01-29
cxl/pci: Skip to handle RAS errors if CXL.mem device is detached
Li Ming
1
-12
/
+31
2023-12-23
cxl: Calculate and store PCI link latency for the downstream ports
Dave Jiang
1
-0
/
+36
2023-12-09
cxl/cdat: Free correct buffer on checksum error
Ira Weiny
1
-7
/
+6
2023-11-03
cxl/pci: Change CXL AER support check to use native AER
Terry Bowman
1
-2
/
+2
2023-10-31
Merge branch 'for-6.7/cxl-qtg' into cxl/next
Dan Williams
1
-12
/
+40
2023-10-28
cxl: Add support for reading CXL switch CDAT table
Dave Jiang
1
-5
/
+17
2023-10-28
cxl: Add checksum verification to CDAT from CXL
Dave Jiang
1
-7
/
+23
2023-10-28
cxl/pci: Disable root port interrupts in RCH mode
Terry Bowman
1
-0
/
+32
2023-10-28
cxl/pci: Add RCH downstream port error logging
Terry Bowman
1
-0
/
+96
2023-10-28
cxl/pci: Map RCH downstream AER registers for logging protocol errors
Terry Bowman
1
-0
/
+36
2023-10-28
cxl/pci: Update CXL error logging to use RAS register address
Terry Bowman
1
-13
/
+31
2023-10-28
cxl/pci: Add RCH downstream port AER register discovery
Robert Richter
1
-0
/
+15
2023-06-26
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
1
-2
/
+2
2023-06-26
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Dan Williams
1
-23
/
+4
2023-06-25
cxl: Rename 'uport' to 'uport_dev'
Dan Williams
1
-2
/
+2
2023-05-19
cxl: Wait Memory_Info_Valid before access memory related info
Dave Jiang
1
-9
/
+76
2023-05-18
cxl/port: Enable the HDM decoder capability for switch ports
Dan Williams
1
-4
/
+23
2023-05-13
cxl: Add missing return to cdat read error path
Dave Jiang
1
-0
/
+1
2023-04-23
cxl/port: Fix port to pci device assumptions in read_cdat_data()
Dan Williams
1
-6
/
+7
2023-04-18
cxl/pci: Rightsize CDAT response allocation
Lukas Wunner
1
-17
/
+19
2023-04-18
cxl/pci: Simplify CDAT retrieval error path
Dave Jiang
1
-11
/
+12
2023-04-18
cxl/pci: Use CDAT DOE mailbox created by PCI core
Lukas Wunner
1
-22
/
+5
2023-04-18
cxl/pci: Use synchronous API for DOE
Lukas Wunner
1
-44
/
+22
2023-04-04
cxl/pci: Handle excessive CDAT length
Lukas Wunner
1
-0
/
+3
2023-04-04
cxl/pci: Handle truncated CDAT entries
Lukas Wunner
1
-4
/
+9
2023-04-04
cxl/pci: Handle truncated CDAT header
Lukas Wunner
1
-1
/
+1
2023-03-21
cxl/pci: Fix CDAT retrieval on big endian
Lukas Wunner
1
-13
/
+13
2023-02-17
Merge branch 'for-6.3/cxl-events' into cxl/next
Dan Williams
1
-6
/
+2
2023-02-17
cxl/trace: Standardize device information output
Ira Weiny
1
-6
/
+2
2023-02-15
Merge branch 'for-6.3/cxl-rr-emu' into cxl/next
Dan Williams
1
-107
/
+93
2023-02-15
cxl/pci: Remove locked check for dvsec_range_allowed()
Dave Jiang
1
-2
/
+0
2023-02-15
cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decoders
Dave Jiang
1
-3
/
+6
2023-02-15
cxl/hdm: Emulate HDM decoder from DVSEC range registers
Dave Jiang
1
-1
/
+1
2023-02-15
cxl/pci: Refactor cxl_hdm_decode_init()
Dave Jiang
1
-81
/
+54
2023-02-15
cxl/port: Export cxl_dvsec_rr_decode() to cxl_port
Dave Jiang
1
-11
/
+7
2023-02-15
cxl/pci: Break out range register decoding from cxl_hdm_decode_init()
Dave Jiang
1
-24
/
+40
2023-02-11
Merge branch 'for-6.3/cxl-ram-region' into cxl/next
Dan Williams
1
-5
/
+0
2023-02-11
kernel/range: Uplevel the cxl subsystem's range_contains() helper
Dan Williams
1
-5
/
+0
2023-02-07
Merge branch 'for-6.3/cxl' into cxl/next
Dan Williams
1
-0
/
+115
2023-01-05
cxl/pci: Move tracepoint definitions to drivers/cxl/core/
Dan Williams
1
-0
/
+112
2022-12-05
Merge branch 'for-6.2/cxl-aer' into for-6.2/cxl
Dan Williams
1
-2
/
+1
2022-12-04
cxl/core/regs: Make cxl_map_{component, device}_regs() device generic
Dan Williams
1
-2
/
+1
2022-11-14
cxl: Unify debug messages when calling devm_cxl_add_dport()
Robert Richter
1
-2
/
+0
2022-07-20
cxl/port: Read CDAT table
Ira Weiny
1
-0
/
+173
2022-07-10
cxl/core: Drop ->platform_res attribute for root decoders
Dan Williams
1
-7
/
+1
2022-05-20
cxl/port: Enable HDM Capability after validating DVSEC Ranges
Dan Williams
1
-15
/
+152
2022-05-19
cxl/port: Reuse 'struct cxl_hdm' context for hdm init
Dan Williams
1
-29
/
+10
2022-05-19
cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Dan Williams
1
-8
/
+7
2022-05-19
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
Dan Williams
1
-7
/
+75
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