Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2022-05-20 | cxl/port: Enable HDM Capability after validating DVSEC Ranges | Dan Williams | 1 | -15/+152 |
2022-05-19 | cxl/port: Reuse 'struct cxl_hdm' context for hdm init | Dan Williams | 1 | -29/+10 |
2022-05-19 | cxl/pci: Drop @info argument to cxl_hdm_decode_init() | Dan Williams | 1 | -8/+7 |
2022-05-19 | cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init() | Dan Williams | 1 | -7/+75 |
2022-05-19 | cxl/mem: Skip range enumeration if mem_enable clear | Dan Williams | 1 | -0/+2 |
2022-05-19 | cxl/mem: Consolidate CXL DVSEC Range enumeration in the core | Dan Williams | 1 | -0/+129 |
2022-05-19 | cxl/pci: Move cxl_await_media_ready() to the core | Dan Williams | 1 | -0/+48 |
2022-02-09 | cxl/core/port: Remove @host argument for dport + decoder enumeration | Dan Williams | 1 | -5/+2 |
2022-02-09 | cxl/port: Add a driver for 'struct cxl_port' objects | Ben Widawsky | 1 | -2/+0 |
2022-02-09 | cxl/core: Generalize dport enumeration in the core | Dan Williams | 1 | -0/+101 |