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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
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fedora-vic-7100_5.10.6
master
openwrt-6.1.y
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starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
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starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
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visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
cxl
/
core
/
port.c
Age
Commit message (
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)
Author
Files
Lines
2024-01-06
Merge branch 'for-6.7/cxl' into for-6.8/cxl
Dan Williams
1
-16
/
+8
2024-01-06
cxl: Convert find_cxl_root() to return a 'struct cxl_root *'
Dave Jiang
1
-2
/
+2
2024-01-06
cxl: Introduce put_cxl_root() helper
Dave Jiang
1
-0
/
+9
2024-01-05
cxl/port: Fix missing target list lock
Dan Williams
1
-15
/
+7
2024-01-05
cxl/port: Fix decoder initialization when nr_targets > interleave_ways
Huang Ying
1
-1
/
+1
2023-12-23
cxl: Add helper function that calculate performance data for downstream ports
Dave Jiang
1
-0
/
+75
2023-12-23
cxl: Calculate and store PCI link latency for the downstream ports
Dave Jiang
1
-0
/
+6
2023-12-23
cxl: Add support for _DSM Function for retrieving QTG ID
Dave Jiang
1
-10
/
+39
2023-12-08
cxl/hdm: Fix dpa translation locking
Dan Williams
1
-2
/
+2
2023-10-31
Merge branch 'for-6.7/cxl-commited' into cxl/next
Dan Williams
1
-0
/
+32
2023-10-31
Merge branch 'for-6.7/cxl' into cxl/next
Dan Williams
1
-1
/
+5
2023-10-31
Merge branch 'for-6.7/cxl-qtg' into cxl/next
Dan Williams
1
-0
/
+11
2023-10-31
Merge branch 'for-6.7/cxl-rch-eh' into cxl/next
Dan Williams
1
-45
/
+84
2023-10-28
cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute
Dave Jiang
1
-0
/
+11
2023-10-28
cxl: Add decoders_committed sysfs attribute to cxl_port
Dave Jiang
1
-0
/
+25
2023-10-28
cxl: Add cxl_decoders_committed() helper
Dave Jiang
1
-0
/
+7
2023-10-28
PCI/AER: Refactor cper_print_aer() for use by CXL driver module
Terry Bowman
1
-0
/
+1
2023-10-28
cxl/port: Remove Component Register base address from struct cxl_port
Robert Richter
1
-3
/
+1
2023-10-28
cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
Robert Richter
1
-7
/
+22
2023-10-28
cxl/port: Pre-initialize component register mappings
Robert Richter
1
-5
/
+7
2023-10-28
cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
Robert Richter
1
-3
/
+3
2023-10-28
cxl/port: Fix @host confusion in cxl_dport_setup_regs()
Dan Williams
1
-12
/
+31
2023-10-28
cxl/core/regs: Rename @dev to @host in struct cxl_register_map
Robert Richter
1
-2
/
+2
2023-10-28
cxl/port: Fix delete_endpoint() vs parent unregistration race
Dan Williams
1
-15
/
+19
2023-10-06
cxl/memdev: Fix sanitize vs decoder setup locking
Dan Williams
1
-0
/
+6
2023-09-23
cxl/port: Fix cxl_test register enumeration regression
Dan Williams
1
-4
/
+9
2023-09-16
cxl/port: Quiet warning messages from the cxl_test environment
Dan Williams
1
-1
/
+6
2023-06-26
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
1
-45
/
+105
2023-06-26
Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl
Dan Williams
1
-0
/
+2
2023-06-26
cxl/memdev: Formalize endpoint port linkage
Dan Williams
1
-2
/
+3
2023-06-26
cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
Dan Williams
1
-3
/
+3
2023-06-25
cxl/port: Store the downstream port's Component Register mappings in struct c...
Robert Richter
1
-0
/
+11
2023-06-25
cxl/port: Store the port's Component Register mappings in struct cxl_port
Robert Richter
1
-0
/
+27
2023-06-25
cxl/pci: Early setup RCH dport component registers from RCRB
Robert Richter
1
-0
/
+7
2023-06-25
cxl/port: Remove Component Register base address from struct cxl_dport
Robert Richter
1
-1
/
+0
2023-06-25
cxl: Rename 'uport' to 'uport_dev'
Dan Williams
1
-28
/
+33
2023-06-25
cxl: Rename member @dport of struct cxl_dport to @dport_dev
Robert Richter
1
-10
/
+10
2023-06-25
cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
Dan Williams
1
-2
/
+2
2023-06-25
cxl/acpi: Probe RCRB later during RCH downstream port creation
Robert Richter
1
-5
/
+16
2023-05-30
cxl/pci: Find and register CXL PMU devices
Jonathan Cameron
1
-0
/
+2
2023-05-20
cxl/port: Fix NULL pointer access in devm_cxl_add_port()
Robert Richter
1
-4
/
+3
2023-04-30
Merge tag 'cxl-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Linus Torvalds
1
-1
/
+0
2023-04-27
Merge tag 'driver-core-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/...
Linus Torvalds
1
-1
/
+1
2023-04-18
cxl/core: Drop unused io-64-nonatomic-lo-hi.h
Dan Williams
1
-1
/
+0
2023-04-05
cxl/port: Fix find_cxl_root() for RCDs and simplify it
Dan Williams
1
-31
/
+7
2023-03-23
driver core: bus: mark the struct bus_type for sysfs callbacks as constant
Greg Kroah-Hartman
1
-1
/
+1
2023-02-25
Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Linus Torvalds
1
-40
/
+83
2023-02-11
Merge branch 'for-6.3/cxl-ram-region' into cxl/next
Dan Williams
1
-39
/
+53
2023-02-11
cxl/dax: Create dax devices for CXL RAM regions
Dan Williams
1
-1
/
+3
2023-02-11
tools/testing/cxl: Define a fixed volatile configuration to parse
Dan Williams
1
-0
/
+2
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