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path: root/drivers/cxl/core/port.c
AgeCommit message (Expand)AuthorFilesLines
2024-01-06Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams1-16/+8
2024-01-06cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-2/+2
2024-01-06cxl: Introduce put_cxl_root() helperDave Jiang1-0/+9
2024-01-05cxl/port: Fix missing target list lockDan Williams1-15/+7
2024-01-05cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying1-1/+1
2023-12-23cxl: Add helper function that calculate performance data for downstream portsDave Jiang1-0/+75
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+6
2023-12-23cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang1-10/+39
2023-12-08cxl/hdm: Fix dpa translation lockingDan Williams1-2/+2
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams1-0/+32
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams1-1/+5
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-0/+11
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams1-45/+84
2023-10-28cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang1-0/+11
2023-10-28cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang1-0/+25
2023-10-28cxl: Add cxl_decoders_committed() helperDave Jiang1-0/+7
2023-10-28PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman1-0/+1
2023-10-28cxl/port: Remove Component Register base address from struct cxl_portRobert Richter1-3/+1
2023-10-28cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter1-7/+22
2023-10-28cxl/port: Pre-initialize component register mappingsRobert Richter1-5/+7
2023-10-28cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter1-3/+3
2023-10-28cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams1-12/+31
2023-10-28cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter1-2/+2
2023-10-28cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams1-15/+19
2023-10-06cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams1-0/+6
2023-09-23cxl/port: Fix cxl_test register enumeration regressionDan Williams1-4/+9
2023-09-16cxl/port: Quiet warning messages from the cxl_test environmentDan Williams1-1/+6
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-45/+105
2023-06-26Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+2
2023-06-26cxl/memdev: Formalize endpoint port linkageDan Williams1-2/+3
2023-06-26cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-3/+3
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter1-0/+11
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter1-0/+27
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-0/+7
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter1-1/+0
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-28/+33
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter1-10/+10
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-2/+2
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-5/+16
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-0/+2
2023-05-20cxl/port: Fix NULL pointer access in devm_cxl_add_port()Robert Richter1-4/+3
2023-04-30Merge tag 'cxl-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds1-1/+0
2023-04-27Merge tag 'driver-core-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-1/+1
2023-04-18cxl/core: Drop unused io-64-nonatomic-lo-hi.hDan Williams1-1/+0
2023-04-05cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams1-31/+7
2023-03-23driver core: bus: mark the struct bus_type for sysfs callbacks as constantGreg Kroah-Hartman1-1/+1
2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds1-40/+83
2023-02-11Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-39/+53
2023-02-11cxl/dax: Create dax devices for CXL RAM regionsDan Williams1-1/+3
2023-02-11tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams1-0/+2
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-03 04:27:21 +0300