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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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log
tree
commit
diff
log msg
author
committer
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path:
root
/
drivers
/
cxl
/
core
Age
Commit message (
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)
Author
Files
Lines
2023-09-23
cxl/port: Fix cxl_test register enumeration regression
Dan Williams
1
-4
/
+9
2023-09-15
cxl/region: Refactor granularity select in cxl_port_setup_targets()
Alison Schofield
1
-9
/
+8
2023-09-15
cxl/region: Match auto-discovered region decoders by HPA range
Alison Schofield
1
-1
/
+23
2023-09-14
cxl/mbox: Fix CEL logic for poison and security commands
Ira Weiny
1
-11
/
+12
2023-07-28
cxl/memdev: Only show sanitize sysfs files when supported
Davidlohr Bueso
2
-1
/
+63
2023-06-30
cxl: Fix one kernel-doc comment
Yang Li
1
-1
/
+1
2023-06-26
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
6
-84
/
+239
2023-06-26
Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl
Dan Williams
5
-6
/
+141
2023-06-26
Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxl
Dan Williams
1
-39
/
+63
2023-06-26
Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl
Dan Williams
8
-262
/
+302
2023-06-26
Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxl
Dan Williams
1
-0
/
+308
2023-06-26
Merge branch 'for-6.5/cxl-background' into for-6.5/cxl
Dan Williams
2
-1
/
+199
2023-06-26
cxl: add a firmware update mechanism using the sysfs firmware loader
Vishal Verma
1
-0
/
+308
2023-06-26
cxl/mem: Support Secure Erase
Davidlohr Bueso
2
-1
/
+33
2023-06-26
cxl/mem: Wire up Sanitization support
Davidlohr Bueso
2
-0
/
+122
2023-06-26
cxl/mbox: Add sanitization handling machinery
Davidlohr Bueso
1
-0
/
+10
2023-06-26
cxl/mem: Introduce security state sysfs file
Davidlohr Bueso
1
-0
/
+33
2023-06-26
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Dan Williams
1
-23
/
+4
2023-06-26
cxl/memdev: Formalize endpoint port linkage
Dan Williams
3
-5
/
+6
2023-06-26
cxl/region: Manage decoder target_type at decoder-attach time
Dan Williams
1
-0
/
+12
2023-06-26
cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
Dan Williams
1
-9
/
+26
2023-06-26
cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
Dan Williams
3
-9
/
+10
2023-06-26
cxl/memdev: Make mailbox functionality optional
Dan Williams
2
-1
/
+10
2023-06-26
cxl/mbox: Move mailbox related driver state to its own data structure
Dan Williams
2
-150
/
+163
2023-06-26
cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output
Dan Williams
1
-4
/
+4
2023-06-25
cxl/region: Fix state transitions after reset failure
Dan Williams
1
-11
/
+15
2023-06-25
cxl/region: Flag partially torn down regions as unusable
Dan Williams
1
-0
/
+12
2023-06-25
cxl/region: Move cache invalidation before region teardown, and before setup
Dan Williams
1
-29
/
+37
2023-06-25
cxl/port: Store the downstream port's Component Register mappings in struct c...
Robert Richter
1
-0
/
+11
2023-06-25
cxl/port: Store the port's Component Register mappings in struct cxl_port
Robert Richter
1
-0
/
+27
2023-06-25
cxl/pci: Early setup RCH dport component registers from RCRB
Robert Richter
1
-0
/
+7
2023-06-25
cxl/regs: Remove early capability checks in Component Register setup
Robert Richter
1
-8
/
+0
2023-06-25
cxl/port: Remove Component Register base address from struct cxl_dport
Robert Richter
1
-1
/
+0
2023-06-25
cxl/pci: Refactor component register discovery for reuse
Terry Bowman
1
-0
/
+77
2023-06-25
cxl/core/regs: Add @dev to cxl_register_map
Robert Richter
2
-8
/
+14
2023-06-25
cxl: Rename 'uport' to 'uport_dev'
Dan Williams
3
-53
/
+60
2023-06-25
cxl: Rename member @dport of struct cxl_dport to @dport_dev
Robert Richter
2
-12
/
+12
2023-06-25
cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
Dan Williams
3
-5
/
+8
2023-06-25
cxl/acpi: Probe RCRB later during RCH downstream port creation
Robert Richter
3
-9
/
+35
2023-05-30
cxl/pci: Find and register CXL PMU devices
Jonathan Cameron
5
-0
/
+88
2023-05-30
cxl: Add functions to get an instance of / count regblocks of a given type
Jonathan Cameron
1
-6
/
+53
2023-05-26
cxl: Explicitly initialize resources when media is not ready
Dave Jiang
1
-6
/
+11
2023-05-23
cxl/mbox: Add background cmd handling machinery
Davidlohr Bueso
1
-1
/
+2
2023-05-20
cxl/port: Fix NULL pointer access in devm_cxl_add_port()
Robert Richter
1
-4
/
+3
2023-05-19
cxl: Move cxl_await_media_ready() to before capacity info retrieval
Dave Jiang
1
-5
/
+10
2023-05-19
cxl: Wait Memory_Info_Valid before access memory related info
Dave Jiang
1
-9
/
+76
2023-05-18
cxl/port: Enable the HDM decoder capability for switch ports
Dan Williams
1
-4
/
+23
2023-05-13
cxl: Add missing return to cdat read error path
Dave Jiang
1
-0
/
+1
2023-04-30
Merge tag 'cxl-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Linus Torvalds
9
-107
/
+793
2023-04-27
Merge tag 'driver-core-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/...
Linus Torvalds
1
-1
/
+1
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