index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
cxl
/
cxlpci.h
Age
Commit message (
Expand
)
Author
Files
Lines
2023-12-23
cxl: Calculate and store PCI link latency for the downstream ports
Dave Jiang
1
-0
/
+13
2023-05-30
cxl/pci: Find and register CXL PMU devices
Jonathan Cameron
1
-0
/
+1
2023-05-19
cxl: Wait Memory_Info_Valid before access memory related info
Dave Jiang
1
-0
/
+2
2023-04-04
cxl/pci: Handle truncated CDAT entries
Lukas Wunner
1
-0
/
+14
2023-02-15
Merge branch 'for-6.3/cxl-rr-emu' into cxl/next
Dan Williams
1
-1
/
+2
2023-02-15
cxl/port: Export cxl_dvsec_rr_decode() to cxl_port
Dave Jiang
1
-1
/
+2
2023-01-27
cxl/mem: Wire up event interrupts
Davidlohr Bueso
1
-0
/
+6
2023-01-05
cxl/pci: Move tracepoint definitions to drivers/cxl/core/
Dan Williams
1
-0
/
+3
2022-12-04
cxl/core/regs: Make cxl_map_{component, device}_regs() device generic
Dan Williams
1
-9
/
+0
2022-07-20
cxl/port: Read CDAT table
Ira Weiny
1
-0
/
+1
2022-05-19
cxl/port: Reuse 'struct cxl_hdm' context for hdm init
Dan Williams
1
-1
/
+1
2022-05-19
cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Dan Williams
1
-3
/
+1
2022-05-19
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
Dan Williams
1
-2
/
+2
2022-05-19
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
Dan Williams
1
-0
/
+4
2022-02-09
cxl/pci: Retrieve CXL DVSEC memory info
Ben Widawsky
1
-0
/
+13
2022-02-09
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
1
-1
/
+1
2022-02-09
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
1
-0
/
+1
2022-02-09
cxl/core: Generalize dport enumeration in the core
Dan Williams
1
-0
/
+1
2022-02-09
cxl/pci: Rename pci.h to cxlpci.h
Dan Williams
1
-0
/
+60